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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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146 lines
7.3 KiB
C
146 lines
7.3 KiB
C
//*****************************************************************************
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//
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// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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// SPDX-License-Identifier: MIT
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS IN THE SOFTWARE.
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//
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// File: nvtiming_pvt.h
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//
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// Purpose: the private functions/structures which are only used inside
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// the nv timing library.
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//
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//*****************************************************************************
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#ifndef __NVTIMING_PVT_H_
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#define __NVTIMING_PVT_H_
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#include "nvtiming.h"
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#if defined(NVT_USE_NVKMS)
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#include "nvidia-modeset-os-interface.h"
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#define NVT_SNPRINTF nvkms_snprintf
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#else
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#include <string.h>
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#include <stdio.h>
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#define NVT_SNPRINTF snprintf
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#endif
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#define nvt_assert(p) ((void)0)
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#include <stddef.h> // NULL
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// EDID related private functions
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NvU32 getEdidVersion(NvU8 *pData, NvU32 *pVer);
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NvBool assignNextAvailableTiming(NVT_EDID_INFO *pInfo, const NVT_TIMING *pTiming);
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void parseEdidCvtTiming(NVT_EDID_INFO *pInfo);
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void parseEdidEstablishedTiming(NVT_EDID_INFO *pInfo);
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void parseEdidStandardTiming(NVT_EDID_INFO *pInfo);
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void parseEdidDetailedTiming(NvU8 *pEdid, NVT_EDID_INFO *pInfo);
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NVT_STATUS parseEdidDetailedTimingDescriptor(NvU8 *pDTD, NVT_TIMING *pT);
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void parseEdidCvt3ByteDescriptor(NvU8 *p, NVT_EDID_INFO *pInfo, NvU32 *vtbCount);
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void parseEdidStandardTimingDescriptor(NvU16 timing, NVT_EDID_INFO *pInfo, NvU32 count, NVT_TIMING * pT);
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void parseVTBExtension(NvU8 *pEdidExt, NVT_EDID_INFO *pInfo);
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void updateHDMILLCDeepColorForTiming(NVT_EDID_INFO *pInfo, NvU32 index);
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void updateBpcForTiming(NVT_EDID_INFO *pInfo, NvU32 index);
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void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo);
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// End EDID
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// CTA861 related private functions
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NVT_STATUS get861ExtInfo(NvU8 *pEdid, NvU32 edidSize, NVT_EDID_CEA861_INFO *p);
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NVT_STATUS parseCta861DataBlockInfo(NvU8 *pEdid, NvU32 size, NVT_EDID_CEA861_INFO *p);
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void parse861ExtDetailedTiming(NvU8 *pEdidExt, NvU8 basicCaps, NVT_EDID_INFO *pInfo);
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void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
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void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
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void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
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void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
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void parseCta861HfScdb(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
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void parseCta861HfEeodb(NVT_EDID_CEA861_INFO *pExt861, NvU32 *pTotalEdidExtensions);
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void parseEdidMsftVsdbBlock(VSDB_DATA *pVsdb, MSFT_VSDB_PARSED_INFO *vsdbInfo);
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void parseEdidHdmiLlcBasicInfo(VSDB_DATA *pVsdb, NVT_HDMI_LLC_INFO *pHdmiLlc);
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void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo);
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void getEdidHDM1_4bVsdbTiming(NVT_EDID_INFO *pInfo);
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void parseEdidHDMILLCTiming(NVT_EDID_INFO *pInfo, VSDB_DATA *pVsdb, NvU32 *pSupported, HDMI3DSUPPORTMAP * pM);
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void parseEdidNvidiaVSDBBlock(VSDB_DATA *pVsdb, NVDA_VSDB_PARSED_INFO *vsdbInfo);
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void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
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void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
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void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
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NvBool isMatchedCTA861Timing(NVT_EDID_INFO *pInfo, NVT_TIMING *pT);
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NvU32 isHdmi3DStereoType(NvU8 StereoStructureType);
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NvU32 getCEA861TimingAspectRatio(NvU32 vic);
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void SetActiveSpaceForHDMI3DStereo(const NVT_TIMING *pTiming, NVT_EXT_TIMING *pExtTiming);
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void AddModeToSupportMap(HDMI3DSUPPORTMAP * pMap, NvU8 vic, NvU8 structure, NvU8 Detail);
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void getMonitorDescriptorString(NvU8 *pEdid, NvU8 tag, char *str, int onceOnly);
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// End CTA861
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// DispalyID base / extension related functions
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NvU32 getDID2Version(NvU8 *pData, NvU32 *pVer);
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NVT_STATUS getDisplayIdEDIDExtInfo(NvU8* pEdid, NvU32 edidSize, NVT_EDID_INFO* pEdidInfo);
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NVT_STATUS parseDisplayIdBlock(NvU8* pBlock, NvU8 max_length, NvU8* pLength, NVT_EDID_INFO* pEdidInfo);
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NVT_STATUS getDisplayId20EDIDExtInfo(NvU8* pDisplayid, NvU32 edidSize, NVT_EDID_INFO* pEdidInfo);
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NVT_STATUS parseDisplayId20EDIDExtDataBlocks(NvU8* pDataBlock, NvU8 remainSectionLength, NvU8* pCurrentDBLength, NVT_EDID_INFO* pEdidInfo);
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void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx);
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void updateColorFormatForDisplayId20ExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx);
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NvBool assignNextAvailableDisplayId20Timing(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, const NVT_TIMING *pTiming);
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void updateColorFormatForDisplayId20Timings(NVT_DISPLAYID_2_0_INFO* pDisplayId2Info, NvU32 timingIdx);
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// End DisplayID
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NvU32 axb_div_c_old(NvU32 a, NvU32 b, NvU32 c);
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#define NVT_EDID_BLOCK_SIZE 128
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#define NVT_PVT_INTERLACED_MASK 0xF
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#define NVT_PVT_DOUBLESCAN_MASK 0x10
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#define NVT_PVT_RB_MASK 0x20
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#define NVT_PVT_DOUBLE_SCAN_HEIGHT 384
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#define NVT_PVT_DOUBLE_SCAN_HEIGHT_VGA 600
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#define NVT_PVT_DOUBLE_SCAN_PCLK_MIN 1200 //in 10KHz
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#define abs(a) ((a)>0?(a):-(a))
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#define set_rrx1k(a,b,c) ((b)*(c)==0?(0):(NvU32)(((NvU64)(a)*10000*1000+(b)*(c)/2)/((b)*(c))))
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#define frame_height(a) ((NvU32)((a).VVisible * ((a).interlaced!=0?2:1)))
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#define nvt_is_wideaspect(width,height) ((width)*5 >= (height)*8)
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#ifndef MIN
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#define MIN(x, y) ((x)>(y) ? (y) : (x))
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#endif
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#ifndef MAX
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#define MAX(x,y) ((x) > (y) ? (x) : (y))
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#endif
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#ifndef COUNT
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#define COUNT(a) (sizeof(a)/sizeof(a[0]))
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#endif
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#ifndef offsetof
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#define offsetof(st, m) ((size_t) ( (char *)&((st *)(0))->m - (char *)0 ))
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#endif
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#define nvt_nvu8_set_bits(d, s, m, shift) {(d)&=(NvU8)((NvU8)(m)^0xFFU);(d)|=((s)<<(shift))&(m);}
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#define nvt_get_bits(d, m, shift) (((d)&(m))>>shift)
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#define nvt_lowest_bit(n) ((n)&(~((n)-1)))
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#define nvt_aspect_x(n) ((n)>>16)
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#define nvt_aspect_y(n) ((n)&0xFFFF)
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// Sentinel values for NVT_TIMING
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#define NVT_TIMINGEXT_SENTINEL {0,0,0,0,0,{0},{0},{0},{0},0,""}
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#define NVT_TIMING_SENTINEL {0,0,0,0,0,0,0,0,0,0,0,0,0,0,NVT_TIMINGEXT_SENTINEL}
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#endif //__NVTIMING_PVT_H_
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