mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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355 lines
10 KiB
C
355 lines
10 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "common_nvswitch.h"
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#include "regkey_nvswitch.h"
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#include "ls10/ls10.h"
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#include "ls10/pmgr_ls10.h"
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#include "error_nvswitch.h"
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#include "pmgr_nvswitch.h"
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#include "rom_nvswitch.h"
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#include "export_nvswitch.h"
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#include "soe/soe_nvswitch.h"
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#include "soe/soeifcore.h"
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#include "nvswitch/ls10/dev_pmgr.h"
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static NvBool
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_nvswitch_i2c_ports_priv_locked_ls10
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(
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nvswitch_device *device
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)
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{
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NvU32 regVal;
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regVal = NVSWITCH_REG_RD32(device, _PMGR, _I2C_PRIV_LEVEL_MASK(NVSWITCH_I2C_PORT_I2CA));
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if (FLD_TEST_DRF(_PMGR, _I2C_PRIV_LEVEL_MASK, _WRITE_PROTECTION_LEVEL0, _DISABLE, regVal))
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{
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return NV_TRUE;
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}
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regVal = NVSWITCH_REG_RD32(device, _PMGR, _I2C_PRIV_LEVEL_MASK(NVSWITCH_I2C_PORT_I2CB));
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if (FLD_TEST_DRF(_PMGR, _I2C_PRIV_LEVEL_MASK, _WRITE_PROTECTION_LEVEL0, _DISABLE, regVal))
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{
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return NV_TRUE;
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}
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regVal = NVSWITCH_REG_RD32(device, _PMGR, _I2C_PRIV_LEVEL_MASK(NVSWITCH_I2C_PORT_I2CC));
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if (FLD_TEST_DRF(_PMGR, _I2C_PRIV_LEVEL_MASK, _WRITE_PROTECTION_LEVEL0, _DISABLE, regVal))
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{
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return NV_TRUE;
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}
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return NV_FALSE;
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}
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static NvlStatus
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_nvswitch_i2c_init_soe_ls10
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(
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nvswitch_device *device
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)
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{
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NvlStatus ret;
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PNVSWITCH_OBJI2C pI2c;
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pI2c = device->pI2c;
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if (!nvswitch_is_soe_supported(device))
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{
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return -NVL_ERR_NOT_SUPPORTED;
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}
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// Setup DMA
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ret = nvswitch_os_alloc_contig_memory(device->os_handle, &pI2c->pCpuAddr, SOE_I2C_DMA_BUF_SIZE,
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(device->dma_addr_width == 32));
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if (ret != NVL_SUCCESS)
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{
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NVSWITCH_PRINT(device, ERROR, "%s: nvswitch_os_alloc_contig_memory returned %d\n", __FUNCTION__, ret);
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return ret;
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}
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nvswitch_os_memset(pI2c->pCpuAddr, 0, SOE_I2C_DMA_BUF_SIZE);
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ret = nvswitch_os_map_dma_region(device->os_handle, pI2c->pCpuAddr, &pI2c->dmaHandle,
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SOE_I2C_DMA_BUF_SIZE, NVSWITCH_DMA_DIR_BIDIRECTIONAL);
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if (ret != NVL_SUCCESS)
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{
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NVSWITCH_PRINT(device, ERROR, "%s: nvswitch_os_map_dma_region returned %d\n", __FUNCTION__, ret);
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nvswitch_os_free_contig_memory(device->os_handle, pI2c->pCpuAddr, SOE_I2C_DMA_BUF_SIZE);
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pI2c->pCpuAddr = NULL;
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return ret;
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}
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return NVL_SUCCESS;
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}
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/*! @brief Set up a port to use a PMGR implementation.
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*
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* @param[in] device NvSwitch device
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* @param[in] port The port identifier for the bus.
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*/
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static void
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_nvswitch_i2c_set_port_pmgr_ls10
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(
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nvswitch_device *device,
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NvU32 port
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)
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{
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PNVSWITCH_OBJI2C pI2c = device->pI2c;
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NVSWITCH_ASSERT(port < NVSWITCH_MAX_I2C_PORTS);
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pI2c->PortInfo[port] = FLD_SET_DRF(_I2C, _PORTINFO, _DEFINED, _PRESENT, pI2c->PortInfo[port]);
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pI2c->Ports[port].defaultSpeedMode = NVSWITCH_I2C_SPEED_MODE_100KHZ;
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pI2c->PortInfo[port] = FLD_SET_DRF(_I2C, _PORTINFO,
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_ACCESS_ALLOWED, _TRUE,
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pI2c->PortInfo[port]);
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}
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//
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// Pre-initialize the software & hardware state of the switch I2C & GPIO interface
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//
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void
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nvswitch_init_pmgr_ls10
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(
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nvswitch_device *device
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)
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{
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PNVSWITCH_OBJI2C pI2c;
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// Initialize I2C object
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nvswitch_i2c_init(device);
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pI2c = device->pI2c;
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if (pI2c != NULL)
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{
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pI2c->kernelI2CSupported = NV_TRUE;
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pI2c->soeI2CSupported = NV_TRUE;
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if (_nvswitch_i2c_ports_priv_locked_ls10(device))
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{
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NVSWITCH_PRINT(device, WARN, "%s: I2C ports priv locked!\n", __FUNCTION__);
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pI2c->kernelI2CSupported = NV_FALSE;
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}
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if (_nvswitch_i2c_init_soe_ls10(device) != NVL_SUCCESS)
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{
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pI2c->soeI2CSupported = NV_FALSE;
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}
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// Setup the 3 I2C ports
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_nvswitch_i2c_set_port_pmgr_ls10(device, NVSWITCH_I2C_PORT_I2CA);
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_nvswitch_i2c_set_port_pmgr_ls10(device, NVSWITCH_I2C_PORT_I2CB);
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_nvswitch_i2c_set_port_pmgr_ls10(device, NVSWITCH_I2C_PORT_I2CC);
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}
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}
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static const NVSWITCH_GPIO_INFO nvswitch_gpio_pin_Default[] =
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{
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NVSWITCH_DESCRIBE_GPIO_PIN( 0, _INSTANCE_ID0, 0, IN), // Instance ID bit 0
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NVSWITCH_DESCRIBE_GPIO_PIN( 1, _INSTANCE_ID1, 0, IN), // Instance ID bit 1
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NVSWITCH_DESCRIBE_GPIO_PIN( 2, _INSTANCE_ID2, 0, IN), // Instance ID bit 2
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};
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static const NvU32 nvswitch_gpio_pin_Default_size = NV_ARRAY_ELEMENTS(nvswitch_gpio_pin_Default);
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//
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// Initialize the software state of the switch I2C & GPIO interface
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// Temporarily forcing default GPIO values.
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//
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// TODO: This function should be updated with the board values from DCB.
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void
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nvswitch_init_pmgr_devices_ls10
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(
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nvswitch_device *device
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)
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{
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ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device);
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PNVSWITCH_OBJI2C pI2c = device->pI2c;
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if (IS_FMODEL(device) || IS_EMULATION(device) || IS_RTLSIM(device))
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{
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// GPIOs not modelled on non-silicon
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chip_device->gpio_pin = NULL;
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chip_device->gpio_pin_size = 0;
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}
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else
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{
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chip_device->gpio_pin = nvswitch_gpio_pin_Default;
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chip_device->gpio_pin_size = nvswitch_gpio_pin_Default_size;
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}
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pI2c->device_list = NULL;
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pI2c->device_list_size = 0;
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}
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NvlStatus
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nvswitch_get_rom_info_ls10
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(
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nvswitch_device *device,
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NVSWITCH_EEPROM_TYPE *eeprom
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)
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{
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NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__);
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return NVL_SUCCESS;
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}
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/*!
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* RM Control command to determine the physical id of the device.
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*/
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NvU32
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nvswitch_read_physical_id_ls10
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(
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nvswitch_device *device
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)
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{
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ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device);
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NvU32 physical_id = 0;
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NvU32 data;
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NvU32 idx_gpio;
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NvU32 input_inv;
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NvU32 function_offset;
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for (idx_gpio = 0; idx_gpio < chip_device->gpio_pin_size; idx_gpio++)
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{
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if ((chip_device->gpio_pin[idx_gpio].function >= NVSWITCH_GPIO_ENTRY_FUNCTION_INSTANCE_ID0) &&
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(chip_device->gpio_pin[idx_gpio].function <= NVSWITCH_GPIO_ENTRY_FUNCTION_INSTANCE_ID6))
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{
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if (chip_device->gpio_pin[idx_gpio].misc == NVSWITCH_GPIO_ENTRY_MISC_IO_INV_IN)
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{
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input_inv = NV_PMGR_GPIO_INPUT_CNTL_1_INV_YES;
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}
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else
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{
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input_inv = NV_PMGR_GPIO_INPUT_CNTL_1_INV_NO;
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}
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NVSWITCH_REG_WR32(device, _PMGR, _GPIO_INPUT_CNTL_1,
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DRF_NUM(_PMGR, _GPIO_INPUT_CNTL_1, _PINNUM, chip_device->gpio_pin[idx_gpio].pin) |
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DRF_NUM(_PMGR, _GPIO_INPUT_CNTL_1, _INV, input_inv) |
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DRF_DEF(_PMGR, _GPIO_INPUT_CNTL_1, _BYPASS_FILTER, _NO));
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data = NVSWITCH_REG_RD32(device, _PMGR, _GPIO_INPUT_CNTL_1);
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function_offset = chip_device->gpio_pin[idx_gpio].function -
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NVSWITCH_GPIO_ENTRY_FUNCTION_INSTANCE_ID0;
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physical_id |=
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(DRF_VAL(_PMGR, _GPIO_INPUT_CNTL_1, _READ, data) << function_offset);
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}
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}
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NVSWITCH_PRINT(device, SETUP, "%s Device position Id = 0x%x\n", __FUNCTION__, physical_id);
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return physical_id;
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}
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/*!
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* RM Control command to perform indexed I2C.
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*/
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NvlStatus
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nvswitch_ctrl_i2c_indexed_ls10
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(
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nvswitch_device *device,
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NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams
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)
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{
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PNVSWITCH_OBJI2C pI2c;
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pI2c = device->pI2c;
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if (pI2c == NULL)
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{
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return -NVL_ERR_NOT_SUPPORTED;
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}
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if (pParams == NULL)
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{
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return -NVL_BAD_ARGS;
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}
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// SW I2C only supported by kernel driver
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if (device->regkeys.force_kernel_i2c == NV_SWITCH_REGKEY_FORCE_KERNEL_I2C_ENABLE ||
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FLD_TEST_DRF(SWITCH_CTRL, _I2C_FLAGS, _FLAVOR, _SW, pParams->flags))
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{
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if (!pI2c->kernelI2CSupported)
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{
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return -NVL_ERR_NOT_SUPPORTED;
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}
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return nvswitch_ctrl_i2c_indexed_lr10(device, pParams);
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}
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if (pParams->port == NVSWITCH_I2C_PORT_I2CA)
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{
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pParams->flags = FLD_SET_DRF(SWITCH_CTRL, _I2C_FLAGS, _SPEED_MODE, _100KHZ, pParams->flags);
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}
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if (pI2c->soeI2CSupported)
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{
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return soeI2CAccess_HAL(device, pParams);
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}
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return -NVL_ERR_NOT_SUPPORTED;
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}
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/*!
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* Return if I2C transactions can be supported.
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*
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* @param[in] device The NvSwitch Device.
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*
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*/
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NvBool
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nvswitch_is_i2c_supported_ls10
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(
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nvswitch_device *device
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)
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{
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return ((device->pI2c != NULL) &&
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(device->pI2c->soeI2CSupported || device->pI2c->kernelI2CSupported));
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}
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/*!
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* Return if I2C device and port is allowed access
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*
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* @param[in] device The NvSwitch Device.
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* @param[in] port The I2C Port.
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* @param[in] addr The I2C device to access.
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* @param[in] bIsRead Boolean if I2C transaction is a read.
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*
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*/
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NvBool
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nvswitch_i2c_is_device_access_allowed_ls10
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(
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nvswitch_device *device,
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NvU32 port,
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NvU8 addr,
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NvBool bIsRead
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)
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{
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// Check will be performed in SOE
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return NV_TRUE;
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}
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