mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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332 lines
12 KiB
C
332 lines
12 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrlc365.finn
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//
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#include "ctrl/ctrlxxxx.h"
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#define NVC365_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC365, NVC365_CTRL_##cat, idx)
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#define NVC365_CTRL_RESERVED (0x00)
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER (0x01)
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/*
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* NVC365_CTRL_CMD_NULL
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*
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* This command does nothing.
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* This command does not take any parameters.
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_NULL (0xc3650000) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET
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*
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* This command provides the value of the GET register
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*
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* accessCntrBufferGetOffset [OUT]
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* This parameter returns the value of the GET register
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET (0xc3650101) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U)
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typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS {
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NvU32 accessCntrBufferGetOffset;
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} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS;
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET
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*
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* This command writes a value into the GET register
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*
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* accessCntrBufferGetValue [IN]
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* This parameter specifies the new value of the GET register
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET (0xc3650102) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U)
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typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS {
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NvU32 accessCntrBufferGetValue;
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} NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS;
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT
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*
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* This command provides the value of the PUT register
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*
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* accessCntrBufferPutOffset [OUT]
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* This parameter returns the value of the PUT register
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT (0xc3650103) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U)
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typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS {
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NvU32 accessCntrBufferPutOffset;
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} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS;
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE
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*
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* This command enables/disables the access counters
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* It also sets up RM to either service or ignore the Access Counter interrupts.
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*
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* intrOwnership [IN]
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* This parameter specifies whether RM should own the interrupt upon return
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* enable [IN]
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* NV_TRUE = Access counters will be enabled
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* NV_FALSE = Access counters will be disabled
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE (0xc3650104) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID (0x4U)
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typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS {
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NvU32 intrOwnership;
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NvBool enable;
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} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS;
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#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NO_CHANGE (0x0)
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#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_RM (0x1)
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#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NOT_RM (0x2)
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE
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*
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* This command provides the size of the notification buffer
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*
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* accessCntrBufferSize [OUT]
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* This parameter returns the size of the notification buffer
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE (0xc3650105) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U)
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typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS {
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NvU32 accessCntrBufferSize;
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} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS;
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS
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*
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* This command provides the access counter register mappings
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*
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* pAccessCntrBufferGet [OUT]
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* This parameter returns the pointer to the GET register
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* pAccessCntrBufferPut [OUT]
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* This parameter returns the pointer to the PUT register
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* pAccessCntrlBufferFull [OUT]
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* This parameter returns the pointer to the FULL register
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* pHubIntr [OUT]
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* This parameter returns the pointer to the hub interrupt register
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* pHubIntrEnSet [OUT]
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* This parameter returns the pointer to the set register
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* pHubIntrEnClear [OUT]
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* This parameter returns the pointer to the clear register
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* accessCntrMask [OUT]
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* This parameter returns the interrupt mask
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS (0xc3650106) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U)
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typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS {
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NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferGet, 8);
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NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferPut, 8);
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NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferFull, 8);
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NV_DECLARE_ALIGNED(NvP64 pHubIntr, 8);
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NV_DECLARE_ALIGNED(NvP64 pHubIntrEnSet, 8);
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NV_DECLARE_ALIGNED(NvP64 pHubIntrEnClear, 8);
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NvU32 accessCntrMask;
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} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS;
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO
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*
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* This command gives information whether the buffer is full
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*
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* fullFlag [OUT]
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* This parameter specifies whether the buffer is full
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO (0xc3650107) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID (0x7U)
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typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS {
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NvBool fullFlag;
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} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS;
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS
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*
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* This command resets access counters of specified type
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*
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* resetFlag [OUT]
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* This parameter specifies that counters have been reset
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* counterType [IN]
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* This parameter specifies the type of counters that should be reset (MIMC, MOMC or ALL)
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS (0xc3650108) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID (0x8U)
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typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS {
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NvBool resetFlag;
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NvU32 counterType;
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} NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS;
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#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MIMC (0x0)
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#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MOMC (0x1)
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#define NVC365_CTRL_ACCESS_COUNTER_TYPE_ALL (0x2)
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG
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*
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* This command configures the access counters
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*
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* mimcGranularity [IN]
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* This parameter specifies the desired granularity for mimc (64K, 2M, 16M, 16G)
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* momcGranularity [IN]
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* This parameter specifies the desired granularity for momc (64K, 2M, 16M, 16G)
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* mimcLimit [IN]
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* This parameter specifies mimc limit (none, qtr, half, full)
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* momcLimit [IN]
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* This parameter specifies momc limit (none, qtr, half, full)
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* threshold [IN]
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* This parameter specifies the threshold
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* flag [IN]
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* This parameter is a bitmask denoting what configurations should be made
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG (0xc3650109) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID (0x9U)
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typedef struct NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS {
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NvU32 mimcGranularity;
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NvU32 momcGranularity;
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NvU32 mimcLimit;
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NvU32 momcLimit;
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NvU32 threshold;
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NvU32 cmd;
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} NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS;
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#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_64K (0x0)
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#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_2M (0x1)
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#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16M (0x2)
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#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16G (0x3)
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#define NVC365_CTRL_ACCESS_COUNTER_MIMC_LIMIT (0x0)
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#define NVC365_CTRL_ACCESS_COUNTER_MOMC_LIMIT (0x1)
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#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_NONE (0x0)
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#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_QTR (0x1)
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#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_HALF (0x2)
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#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_FULL (0x3)
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#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_GRANULARITY (0x1)
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#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_GRANULARITY (0x2)
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#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_LIMIT (0x4)
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#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_LIMIT (0x8)
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#define NVC365_CTRL_ACCESS_COUNTER_SET_THRESHOLD (0x10)
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/*
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* NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR
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*
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* This command enables the access counters interrupts
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*
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* enable [OUT]
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* This parameter specifies that the access counters interrupts are enabled
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR (0xc365010b) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID" */
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#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID (0xBU)
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typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS {
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NvBool enable;
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} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS;
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/* _ctrlc365_h_ */
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