mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-01-30 21:19:49 +00:00
2114 lines
65 KiB
C
2114 lines
65 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* WARNING: This is an autogenerated file. DO NOT EDIT.
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* This file is generated using below files:
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* template file: kernel/inc/vgpu/gt_rpc-structures.h
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* definition file: kernel/inc/vgpu/rpc-structures.def
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*/
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#ifdef RPC_STRUCTURES
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// These structures will be used for the communication between the vmioplugin & guest RM.
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#define SDK_STRUCTURES
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#include "g_sdk-structures.h"
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#undef SDK_STRUCTURES
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typedef struct rpc_set_guest_system_info_v03_00
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{
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NvU32 vgxVersionMajorNum;
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NvU32 vgxVersionMinorNum;
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NvU32 guestDriverVersionBufferLength;
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NvU32 guestVersionBufferLength;
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NvU32 guestTitleBufferLength;
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NvU32 guestClNum;
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char guestDriverVersion[0x100];
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char guestVersion[0x100];
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char guestTitle[0x100];
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} rpc_set_guest_system_info_v03_00;
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typedef rpc_set_guest_system_info_v03_00 rpc_set_guest_system_info_v;
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typedef struct rpc_alloc_memory_v13_01
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{
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NvHandle hClient;
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NvHandle hDevice;
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NvHandle hMemory;
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NvU32 hClass;
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NvU32 flags;
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NvU32 pteAdjust;
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NvU32 format;
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NvU64 length NV_ALIGN_BYTES(8);
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NvU32 pageCount;
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struct pte_desc pteDesc;
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} rpc_alloc_memory_v13_01;
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typedef rpc_alloc_memory_v13_01 rpc_alloc_memory_v;
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typedef struct rpc_free_v03_00
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{
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NVOS00_PARAMETERS_v03_00 params;
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} rpc_free_v03_00;
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typedef rpc_free_v03_00 rpc_free_v;
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typedef struct rpc_map_memory_dma_v03_00
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{
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NVOS46_PARAMETERS_v03_00 params;
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} rpc_map_memory_dma_v03_00;
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typedef rpc_map_memory_dma_v03_00 rpc_map_memory_dma_v;
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typedef struct rpc_unmap_memory_dma_v03_00
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{
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NVOS47_PARAMETERS_v03_00 params;
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} rpc_unmap_memory_dma_v03_00;
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typedef rpc_unmap_memory_dma_v03_00 rpc_unmap_memory_dma_v;
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typedef struct rpc_dup_object_v03_00
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{
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NVOS55_PARAMETERS_v03_00 params;
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} rpc_dup_object_v03_00;
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typedef rpc_dup_object_v03_00 rpc_dup_object_v;
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typedef struct rpc_idle_channels_v03_00
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{
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NvU32 flags;
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NvU32 timeout;
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NvU32 nchannels;
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idle_channel_list_v03_00 channel_list[];
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} rpc_idle_channels_v03_00;
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typedef rpc_idle_channels_v03_00 rpc_idle_channels_v;
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typedef struct rpc_unloading_guest_driver_v1F_07
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{
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NvBool bSuspend;
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NvBool bGc6Entering;
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NvU32 newLevel;
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} rpc_unloading_guest_driver_v1F_07;
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typedef rpc_unloading_guest_driver_v1F_07 rpc_unloading_guest_driver_v;
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typedef struct rpc_gpu_exec_reg_ops_v12_01
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{
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NvHandle hClient;
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NvHandle hObject;
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gpu_exec_reg_ops_v12_01 params;
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} rpc_gpu_exec_reg_ops_v12_01;
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typedef rpc_gpu_exec_reg_ops_v12_01 rpc_gpu_exec_reg_ops_v;
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typedef struct rpc_set_page_directory_v03_00
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{
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NvHandle hClient;
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NvHandle hDevice;
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NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00 params;
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} rpc_set_page_directory_v03_00;
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typedef struct rpc_set_page_directory_v1E_05
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{
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NvHandle hClient;
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NvHandle hDevice;
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NvU32 pasid;
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NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 params;
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} rpc_set_page_directory_v1E_05;
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typedef rpc_set_page_directory_v1E_05 rpc_set_page_directory_v;
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typedef struct rpc_unset_page_directory_v03_00
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{
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NvHandle hClient;
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NvHandle hDevice;
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NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00 params;
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} rpc_unset_page_directory_v03_00;
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typedef struct rpc_unset_page_directory_v1E_05
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{
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NvHandle hClient;
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NvHandle hDevice;
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NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 params;
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} rpc_unset_page_directory_v1E_05;
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typedef rpc_unset_page_directory_v1E_05 rpc_unset_page_directory_v;
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typedef struct rpc_get_gsp_static_info_v14_00
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{
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NvU32 data;
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} rpc_get_gsp_static_info_v14_00;
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typedef rpc_get_gsp_static_info_v14_00 rpc_get_gsp_static_info_v;
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typedef struct rpc_update_bar_pde_v15_00
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{
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UpdateBarPde_v15_00 info;
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} rpc_update_bar_pde_v15_00;
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typedef rpc_update_bar_pde_v15_00 rpc_update_bar_pde_v;
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typedef struct rpc_vgpu_pf_reg_read32_v15_00
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{
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NvU64 address NV_ALIGN_BYTES(8);
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NvU32 value;
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NvU32 grEngId;
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} rpc_vgpu_pf_reg_read32_v15_00;
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typedef rpc_vgpu_pf_reg_read32_v15_00 rpc_vgpu_pf_reg_read32_v;
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typedef struct rpc_rmfs_init_v15_00
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{
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NvU64 statusQueuePhysAddr NV_ALIGN_BYTES(8);
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} rpc_rmfs_init_v15_00;
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typedef rpc_rmfs_init_v15_00 rpc_rmfs_init_v;
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typedef struct rpc_rmfs_test_v15_00
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{
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NvU32 numReps;
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NvU32 flags;
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NvU32 testData1;
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NvU32 testData2;
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} rpc_rmfs_test_v15_00;
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typedef rpc_rmfs_test_v15_00 rpc_rmfs_test_v;
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typedef struct rpc_gsp_set_system_info_v17_00
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{
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NvU32 data;
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} rpc_gsp_set_system_info_v17_00;
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typedef rpc_gsp_set_system_info_v17_00 rpc_gsp_set_system_info_v;
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typedef struct rpc_gsp_rm_alloc_v03_00
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{
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NvHandle hClient;
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NvHandle hParent;
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NvHandle hObject;
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NvU32 hClass;
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NvU32 status;
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NvU32 paramsSize;
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NvU8 params[];
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} rpc_gsp_rm_alloc_v03_00;
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typedef rpc_gsp_rm_alloc_v03_00 rpc_gsp_rm_alloc_v;
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typedef struct rpc_gsp_rm_control_v03_00
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{
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NvHandle hClient;
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NvHandle hObject;
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NvU32 cmd;
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NvU32 status;
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NvU32 paramsSize;
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NvBool serialized;
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NvU8 reserved[3];
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NvU8 params[];
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} rpc_gsp_rm_control_v03_00;
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typedef rpc_gsp_rm_control_v03_00 rpc_gsp_rm_control_v;
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typedef struct rpc_dump_protobuf_component_v18_12
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{
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NvU16 component;
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NvU8 nvDumpType;
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NvBool countOnly;
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NvU32 bugCheckCode;
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NvU32 internalCode;
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NvU32 bufferSize;
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NvU8 blob[];
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} rpc_dump_protobuf_component_v18_12;
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typedef rpc_dump_protobuf_component_v18_12 rpc_dump_protobuf_component_v;
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typedef struct rpc_run_cpu_sequencer_v17_00
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{
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NvU32 bufferSizeDWord;
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NvU32 cmdIndex;
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NvU32 regSaveArea[8];
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NvU32 commandBuffer[];
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} rpc_run_cpu_sequencer_v17_00;
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typedef rpc_run_cpu_sequencer_v17_00 rpc_run_cpu_sequencer_v;
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typedef struct rpc_post_event_v17_00
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{
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NvHandle hClient;
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NvHandle hEvent;
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NvU32 notifyIndex;
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NvU32 data;
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NvU32 status;
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NvU32 eventDataSize;
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NvBool bNotifyList;
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NvU8 eventData[];
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} rpc_post_event_v17_00;
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typedef rpc_post_event_v17_00 rpc_post_event_v;
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typedef struct rpc_rc_triggered_v17_02
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{
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NvU32 nv2080EngineType;
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NvU32 chid;
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NvU32 exceptType;
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NvU32 scope;
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NvU16 partitionAttributionId;
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} rpc_rc_triggered_v17_02;
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typedef rpc_rc_triggered_v17_02 rpc_rc_triggered_v;
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typedef struct rpc_os_error_log_v17_00
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{
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NvU32 exceptType;
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NvU32 runlistId;
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NvU32 chid;
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char errString[0x100];
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} rpc_os_error_log_v17_00;
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typedef rpc_os_error_log_v17_00 rpc_os_error_log_v;
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typedef struct rpc_rg_line_intr_v17_00
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{
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NvU32 head;
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NvU32 rgIntr;
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} rpc_rg_line_intr_v17_00;
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typedef rpc_rg_line_intr_v17_00 rpc_rg_line_intr_v;
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typedef struct rpc_display_modeset_v01_00
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{
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NvBool bModesetStart;
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NvU32 minRequiredIsoBandwidthKBPS;
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NvU32 minRequiredFloorBandwidthKBPS;
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} rpc_display_modeset_v01_00;
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typedef rpc_display_modeset_v01_00 rpc_display_modeset_v;
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typedef struct rpc_gpuacct_perfmon_util_samples_v17_00
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{
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NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00 params;
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} rpc_gpuacct_perfmon_util_samples_v17_00;
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typedef rpc_gpuacct_perfmon_util_samples_v17_00 rpc_gpuacct_perfmon_util_samples_v;
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typedef struct rpc_vgpu_gsp_plugin_triggered_v17_00
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{
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NvU32 gfid;
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NvU32 notifyIndex;
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} rpc_vgpu_gsp_plugin_triggered_v17_00;
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typedef rpc_vgpu_gsp_plugin_triggered_v17_00 rpc_vgpu_gsp_plugin_triggered_v;
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typedef struct rpc_vgpu_config_event_v17_00
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{
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NvU32 notifyIndex;
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} rpc_vgpu_config_event_v17_00;
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typedef rpc_vgpu_config_event_v17_00 rpc_vgpu_config_event_v;
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typedef struct rpc_dce_rm_init_v01_00
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{
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NvBool bInit;
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} rpc_dce_rm_init_v01_00;
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typedef rpc_dce_rm_init_v01_00 rpc_dce_rm_init_v;
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typedef struct rpc_sim_read_v1E_01
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{
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char path[0x100];
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NvU32 index;
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NvU32 count;
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} rpc_sim_read_v1E_01;
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typedef rpc_sim_read_v1E_01 rpc_sim_read_v;
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typedef struct rpc_sim_write_v1E_01
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{
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char path[0x100];
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NvU32 index;
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NvU32 count;
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NvU32 data;
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} rpc_sim_write_v1E_01;
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typedef rpc_sim_write_v1E_01 rpc_sim_write_v;
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typedef struct rpc_ucode_libos_print_v1E_08
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{
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NvU32 ucodeEngDesc;
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NvU32 libosPrintBufSize;
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NvU8 libosPrintBuf[];
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} rpc_ucode_libos_print_v1E_08;
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typedef rpc_ucode_libos_print_v1E_08 rpc_ucode_libos_print_v;
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typedef struct rpc_init_done_v17_00
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{
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NvU32 not_used;
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} rpc_init_done_v17_00;
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typedef rpc_init_done_v17_00 rpc_init_done_v;
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typedef struct rpc_semaphore_schedule_callback_v17_00
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{
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NvU64 GPUVA NV_ALIGN_BYTES(8);
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NvU32 hVASpace;
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NvU32 ReleaseValue;
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NvU32 Flags;
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NvU32 completionStatus;
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NvHandle hClient;
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NvHandle hEvent;
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} rpc_semaphore_schedule_callback_v17_00;
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typedef rpc_semaphore_schedule_callback_v17_00 rpc_semaphore_schedule_callback_v;
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typedef struct rpc_perf_gpu_boost_sync_limits_callback_v17_00
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{
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NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 params;
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} rpc_perf_gpu_boost_sync_limits_callback_v17_00;
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typedef rpc_perf_gpu_boost_sync_limits_callback_v17_00 rpc_perf_gpu_boost_sync_limits_callback_v;
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typedef struct rpc_perf_bridgeless_info_update_v17_00
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{
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NvU64 bBridgeless NV_ALIGN_BYTES(8);
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} rpc_perf_bridgeless_info_update_v17_00;
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typedef rpc_perf_bridgeless_info_update_v17_00 rpc_perf_bridgeless_info_update_v;
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#endif
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#ifdef RPC_DEBUG_PRINT_STRUCTURES
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// These are printable definitions of above structures. These will be used for RPC logging in the vmioplugin.
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#define SDK_DEBUG_PRINT_STRUCTURES
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#include "g_sdk-structures.h"
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#undef SDK_DEBUG_PRINT_STRUCTURES
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#ifndef SKIP_PRINT_rpc_nop_v03_00
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static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nop_v03_00[] = {
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{
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.vtype = vt_end
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}
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};
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static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nop_v03_00 = {
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.name = "rpc_nop",
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.fdesc = vmiopd_fdesc_t_rpc_nop_v03_00
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};
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#endif
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#ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00
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static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00[] = {
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{
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.vtype = vtype_NvU32,
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.offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMajorNum),
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.name = "vgxVersionMajorNum"
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},
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{
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.vtype = vtype_NvU32,
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.offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMinorNum),
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.name = "vgxVersionMinorNum"
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},
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{
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.vtype = vtype_NvU32,
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.offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersionBufferLength),
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.name = "guestDriverVersionBufferLength"
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},
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{
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.vtype = vtype_NvU32,
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.offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersionBufferLength),
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.name = "guestVersionBufferLength"
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},
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{
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.vtype = vtype_NvU32,
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.offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitleBufferLength),
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.name = "guestTitleBufferLength"
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},
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{
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.vtype = vtype_NvU32,
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.offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestClNum),
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.name = "guestClNum"
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},
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{
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.vtype = vtype_char_array,
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.offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersion),
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.array_length = 0x100,
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.name = "guestDriverVersion"
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},
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{
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.vtype = vtype_char_array,
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.offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersion),
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.array_length = 0x100,
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.name = "guestVersion"
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},
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{
|
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.vtype = vtype_char_array,
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.offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitle),
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.array_length = 0x100,
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.name = "guestTitle"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00 = {
|
|
.name = "rpc_set_guest_system_info",
|
|
.header_length = NV_SIZEOF32(rpc_set_guest_system_info_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_alloc_memory_v13_01
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_memory_v13_01[] = {
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hDevice),
|
|
.name = "hDevice"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hMemory),
|
|
.name = "hMemory"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClass),
|
|
.name = "hClass"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, flags),
|
|
.name = "flags"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteAdjust),
|
|
.name = "pteAdjust"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, format),
|
|
.name = "format"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU64,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, length),
|
|
.name = "length"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pageCount),
|
|
.name = "pageCount"
|
|
},
|
|
{
|
|
.vtype = vtype_struct_pte_desc,
|
|
.offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteDesc),
|
|
.name = "pteDesc"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_memory_v13_01 = {
|
|
.name = "rpc_alloc_memory",
|
|
.header_length = NV_SIZEOF32(rpc_alloc_memory_v13_01),
|
|
.fdesc = vmiopd_fdesc_t_rpc_alloc_memory_v13_01
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_free_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_free_v03_00[] = {
|
|
{
|
|
.vtype = vtype_NVOS00_PARAMETERS_v03_00,
|
|
.offset = NV_OFFSETOF(rpc_free_v03_00, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_free_v03_00 = {
|
|
.name = "rpc_free",
|
|
.header_length = NV_SIZEOF32(rpc_free_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_free_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_map_memory_dma_v03_00[] = {
|
|
{
|
|
.vtype = vtype_NVOS46_PARAMETERS_v03_00,
|
|
.offset = NV_OFFSETOF(rpc_map_memory_dma_v03_00, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_map_memory_dma_v03_00 = {
|
|
.name = "rpc_map_memory_dma",
|
|
.header_length = NV_SIZEOF32(rpc_map_memory_dma_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_map_memory_dma_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00[] = {
|
|
{
|
|
.vtype = vtype_NVOS47_PARAMETERS_v03_00,
|
|
.offset = NV_OFFSETOF(rpc_unmap_memory_dma_v03_00, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00 = {
|
|
.name = "rpc_unmap_memory_dma",
|
|
.header_length = NV_SIZEOF32(rpc_unmap_memory_dma_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_dup_object_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dup_object_v03_00[] = {
|
|
{
|
|
.vtype = vtype_NVOS55_PARAMETERS_v03_00,
|
|
.offset = NV_OFFSETOF(rpc_dup_object_v03_00, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dup_object_v03_00 = {
|
|
.name = "rpc_dup_object",
|
|
.header_length = NV_SIZEOF32(rpc_dup_object_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_dup_object_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_idle_channels_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_idle_channels_v03_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_idle_channels_v03_00, flags),
|
|
.name = "flags"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_idle_channels_v03_00, timeout),
|
|
.name = "timeout"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_idle_channels_v03_00, nchannels),
|
|
.name = "nchannels"
|
|
},
|
|
{
|
|
.vtype = vtype_idle_channel_list_v03_00_array,
|
|
.offset = NV_OFFSETOF(rpc_idle_channels_v03_00, channel_list),
|
|
.array_length = 0,
|
|
.array_length_fn = get_array_length_rpc_idle_channels_v03_00_channel_list,
|
|
.name = "channel_list"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_idle_channels_v03_00 = {
|
|
.name = "rpc_idle_channels",
|
|
.header_length = NV_SIZEOF32(rpc_idle_channels_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_idle_channels_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v03_00[] = {
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v03_00 = {
|
|
.name = "rpc_unloading_guest_driver",
|
|
.fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07[] = {
|
|
{
|
|
.vtype = vtype_NvBool,
|
|
.offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bSuspend),
|
|
.name = "bSuspend"
|
|
},
|
|
{
|
|
.vtype = vtype_NvBool,
|
|
.offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bGc6Entering),
|
|
.name = "bGc6Entering"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, newLevel),
|
|
.name = "newLevel"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07 = {
|
|
.name = "rpc_unloading_guest_driver",
|
|
.header_length = NV_SIZEOF32(rpc_unloading_guest_driver_v1F_07),
|
|
.fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01[] = {
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hObject),
|
|
.name = "hObject"
|
|
},
|
|
{
|
|
.vtype = vtype_gpu_exec_reg_ops_v12_01,
|
|
.offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01 = {
|
|
.name = "rpc_gpu_exec_reg_ops",
|
|
.header_length = NV_SIZEOF32(rpc_gpu_exec_reg_ops_v12_01),
|
|
.fdesc = vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v1E_05[] = {
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hDevice),
|
|
.name = "hDevice"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, pasid),
|
|
.name = "pasid"
|
|
},
|
|
{
|
|
.vtype = vtype_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05,
|
|
.offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v1E_05 = {
|
|
.name = "rpc_set_page_directory",
|
|
.header_length = NV_SIZEOF32(rpc_set_page_directory_v1E_05),
|
|
.fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v1E_05
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_set_page_directory_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v03_00[] = {
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_set_page_directory_v03_00, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_set_page_directory_v03_00, hDevice),
|
|
.name = "hDevice"
|
|
},
|
|
{
|
|
.vtype = vtype_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00,
|
|
.offset = NV_OFFSETOF(rpc_set_page_directory_v03_00, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v03_00 = {
|
|
.name = "rpc_set_page_directory",
|
|
.header_length = NV_SIZEOF32(rpc_set_page_directory_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05[] = {
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hDevice),
|
|
.name = "hDevice"
|
|
},
|
|
{
|
|
.vtype = vtype_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05,
|
|
.offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05 = {
|
|
.name = "rpc_unset_page_directory",
|
|
.header_length = NV_SIZEOF32(rpc_unset_page_directory_v1E_05),
|
|
.fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unset_page_directory_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v03_00[] = {
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_unset_page_directory_v03_00, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_unset_page_directory_v03_00, hDevice),
|
|
.name = "hDevice"
|
|
},
|
|
{
|
|
.vtype = vtype_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00,
|
|
.offset = NV_OFFSETOF(rpc_unset_page_directory_v03_00, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v03_00 = {
|
|
.name = "rpc_unset_page_directory",
|
|
.header_length = NV_SIZEOF32(rpc_unset_page_directory_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_get_gsp_static_info_v14_00, data),
|
|
.name = "data"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00 = {
|
|
.name = "rpc_get_gsp_static_info",
|
|
.header_length = NV_SIZEOF32(rpc_get_gsp_static_info_v14_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_update_bar_pde_v15_00[] = {
|
|
{
|
|
.vtype = vtype_UpdateBarPde_v15_00,
|
|
.offset = NV_OFFSETOF(rpc_update_bar_pde_v15_00, info),
|
|
.name = "info"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_update_bar_pde_v15_00 = {
|
|
.name = "rpc_update_bar_pde",
|
|
.header_length = NV_SIZEOF32(rpc_update_bar_pde_v15_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_update_bar_pde_v15_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00[] = {
|
|
{
|
|
.vtype = vtype_NvU64,
|
|
.offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, address),
|
|
.name = "address"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, value),
|
|
.name = "value"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, grEngId),
|
|
.name = "grEngId"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00 = {
|
|
.name = "rpc_vgpu_pf_reg_read32",
|
|
.header_length = NV_SIZEOF32(rpc_vgpu_pf_reg_read32_v15_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rmfs_init_v15_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_init_v15_00[] = {
|
|
{
|
|
.vtype = vtype_NvU64,
|
|
.offset = NV_OFFSETOF(rpc_rmfs_init_v15_00, statusQueuePhysAddr),
|
|
.name = "statusQueuePhysAddr"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_init_v15_00 = {
|
|
.name = "rpc_rmfs_init",
|
|
.header_length = NV_SIZEOF32(rpc_rmfs_init_v15_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_rmfs_init_v15_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rmfs_close_queue_v15_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_close_queue_v15_00[] = {
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_close_queue_v15_00 = {
|
|
.name = "rpc_rmfs_close_queue",
|
|
.fdesc = vmiopd_fdesc_t_rpc_rmfs_close_queue_v15_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rmfs_cleanup_v15_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_cleanup_v15_00[] = {
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_cleanup_v15_00 = {
|
|
.name = "rpc_rmfs_cleanup",
|
|
.fdesc = vmiopd_fdesc_t_rpc_rmfs_cleanup_v15_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rmfs_test_v15_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_test_v15_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, numReps),
|
|
.name = "numReps"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, flags),
|
|
.name = "flags"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, testData1),
|
|
.name = "testData1"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, testData2),
|
|
.name = "testData2"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_test_v15_00 = {
|
|
.name = "rpc_rmfs_test",
|
|
.header_length = NV_SIZEOF32(rpc_rmfs_test_v15_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_rmfs_test_v15_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_gsp_set_system_info_v17_00, data),
|
|
.name = "data"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_set_system_info_v17_00 = {
|
|
.name = "rpc_gsp_set_system_info",
|
|
.header_length = NV_SIZEOF32(rpc_gsp_set_system_info_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_set_registry_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_registry_v17_00[] = {
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_registry_v17_00 = {
|
|
.name = "rpc_set_registry",
|
|
.fdesc = vmiopd_fdesc_t_rpc_set_registry_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gsp_rm_alloc_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00[] = {
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hParent),
|
|
.name = "hParent"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hObject),
|
|
.name = "hObject"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClass),
|
|
.name = "hClass"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, status),
|
|
.name = "status"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, paramsSize),
|
|
.name = "paramsSize"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU8_array,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, params),
|
|
.array_length = 0,
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_alloc_v03_00 = {
|
|
.name = "rpc_gsp_rm_alloc",
|
|
.header_length = NV_SIZEOF32(rpc_gsp_rm_alloc_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gsp_rm_control_v03_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00[] = {
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hObject),
|
|
.name = "hObject"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, cmd),
|
|
.name = "cmd"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, status),
|
|
.name = "status"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, paramsSize),
|
|
.name = "paramsSize"
|
|
},
|
|
{
|
|
.vtype = vtype_NvBool,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, serialized),
|
|
.name = "serialized"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU8_array,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, reserved),
|
|
.array_length = 3,
|
|
.name = "reserved"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU8_array,
|
|
.offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, params),
|
|
.array_length = 0,
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_control_v03_00 = {
|
|
.name = "rpc_gsp_rm_control",
|
|
.header_length = NV_SIZEOF32(rpc_gsp_rm_control_v03_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_dump_protobuf_component_v18_12
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12[] = {
|
|
{
|
|
.vtype = vtype_NvU16,
|
|
.offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, component),
|
|
.name = "component"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU8,
|
|
.offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, nvDumpType),
|
|
.name = "nvDumpType"
|
|
},
|
|
{
|
|
.vtype = vtype_NvBool,
|
|
.offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, countOnly),
|
|
.name = "countOnly"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bugCheckCode),
|
|
.name = "bugCheckCode"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, internalCode),
|
|
.name = "internalCode"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bufferSize),
|
|
.name = "bufferSize"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU8_array,
|
|
.offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, blob),
|
|
.array_length = 0,
|
|
.name = "blob"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dump_protobuf_component_v18_12 = {
|
|
.name = "rpc_dump_protobuf_component",
|
|
.header_length = NV_SIZEOF32(rpc_dump_protobuf_component_v18_12),
|
|
.fdesc = vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_run_cpu_sequencer_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, bufferSizeDWord),
|
|
.name = "bufferSizeDWord"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, cmdIndex),
|
|
.name = "cmdIndex"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32_array,
|
|
.offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, regSaveArea),
|
|
.array_length = 8,
|
|
.name = "regSaveArea"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32_array,
|
|
.offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, commandBuffer),
|
|
.array_length = 0,
|
|
.name = "commandBuffer"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_run_cpu_sequencer_v17_00 = {
|
|
.name = "rpc_run_cpu_sequencer",
|
|
.header_length = NV_SIZEOF32(rpc_run_cpu_sequencer_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_post_event_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_post_event_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_post_event_v17_00, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_post_event_v17_00, hEvent),
|
|
.name = "hEvent"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_post_event_v17_00, notifyIndex),
|
|
.name = "notifyIndex"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_post_event_v17_00, data),
|
|
.name = "data"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_post_event_v17_00, status),
|
|
.name = "status"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_post_event_v17_00, eventDataSize),
|
|
.name = "eventDataSize"
|
|
},
|
|
{
|
|
.vtype = vtype_NvBool,
|
|
.offset = NV_OFFSETOF(rpc_post_event_v17_00, bNotifyList),
|
|
.name = "bNotifyList"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU8_array,
|
|
.offset = NV_OFFSETOF(rpc_post_event_v17_00, eventData),
|
|
.array_length = 0,
|
|
.name = "eventData"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_post_event_v17_00 = {
|
|
.name = "rpc_post_event",
|
|
.header_length = NV_SIZEOF32(rpc_post_event_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_post_event_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rc_triggered_v17_02
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rc_triggered_v17_02[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, nv2080EngineType),
|
|
.name = "nv2080EngineType"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, chid),
|
|
.name = "chid"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, exceptType),
|
|
.name = "exceptType"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, scope),
|
|
.name = "scope"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU16,
|
|
.offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, partitionAttributionId),
|
|
.name = "partitionAttributionId"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rc_triggered_v17_02 = {
|
|
.name = "rpc_rc_triggered",
|
|
.header_length = NV_SIZEOF32(rpc_rc_triggered_v17_02),
|
|
.fdesc = vmiopd_fdesc_t_rpc_rc_triggered_v17_02
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_os_error_log_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_os_error_log_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_os_error_log_v17_00, exceptType),
|
|
.name = "exceptType"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_os_error_log_v17_00, runlistId),
|
|
.name = "runlistId"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_os_error_log_v17_00, chid),
|
|
.name = "chid"
|
|
},
|
|
{
|
|
.vtype = vtype_char_array,
|
|
.offset = NV_OFFSETOF(rpc_os_error_log_v17_00, errString),
|
|
.array_length = 0x100,
|
|
.name = "errString"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_os_error_log_v17_00 = {
|
|
.name = "rpc_os_error_log",
|
|
.header_length = NV_SIZEOF32(rpc_os_error_log_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_os_error_log_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rg_line_intr_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rg_line_intr_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, head),
|
|
.name = "head"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, rgIntr),
|
|
.name = "rgIntr"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rg_line_intr_v17_00 = {
|
|
.name = "rpc_rg_line_intr",
|
|
.header_length = NV_SIZEOF32(rpc_rg_line_intr_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_rg_line_intr_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_display_modeset_v01_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_display_modeset_v01_00[] = {
|
|
{
|
|
.vtype = vtype_NvBool,
|
|
.offset = NV_OFFSETOF(rpc_display_modeset_v01_00, bModesetStart),
|
|
.name = "bModesetStart"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredIsoBandwidthKBPS),
|
|
.name = "minRequiredIsoBandwidthKBPS"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredFloorBandwidthKBPS),
|
|
.name = "minRequiredFloorBandwidthKBPS"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_display_modeset_v01_00 = {
|
|
.name = "rpc_display_modeset",
|
|
.header_length = NV_SIZEOF32(rpc_display_modeset_v01_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_display_modeset_v01_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00,
|
|
.offset = NV_OFFSETOF(rpc_gpuacct_perfmon_util_samples_v17_00, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00 = {
|
|
.name = "rpc_gpuacct_perfmon_util_samples",
|
|
.header_length = NV_SIZEOF32(rpc_gpuacct_perfmon_util_samples_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_vgpu_gsp_plugin_triggered_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, gfid),
|
|
.name = "gfid"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, notifyIndex),
|
|
.name = "notifyIndex"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 = {
|
|
.name = "rpc_vgpu_gsp_plugin_triggered",
|
|
.header_length = NV_SIZEOF32(rpc_vgpu_gsp_plugin_triggered_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_vgpu_config_event_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_vgpu_config_event_v17_00, notifyIndex),
|
|
.name = "notifyIndex"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_config_event_v17_00 = {
|
|
.name = "rpc_vgpu_config_event",
|
|
.header_length = NV_SIZEOF32(rpc_vgpu_config_event_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_dce_rm_init_v01_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dce_rm_init_v01_00[] = {
|
|
{
|
|
.vtype = vtype_NvBool,
|
|
.offset = NV_OFFSETOF(rpc_dce_rm_init_v01_00, bInit),
|
|
.name = "bInit"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dce_rm_init_v01_00 = {
|
|
.name = "rpc_dce_rm_init",
|
|
.header_length = NV_SIZEOF32(rpc_dce_rm_init_v01_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_dce_rm_init_v01_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_sim_read_v1E_01
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_read_v1E_01[] = {
|
|
{
|
|
.vtype = vtype_char_array,
|
|
.offset = NV_OFFSETOF(rpc_sim_read_v1E_01, path),
|
|
.array_length = 0x100,
|
|
.name = "path"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_sim_read_v1E_01, index),
|
|
.name = "index"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_sim_read_v1E_01, count),
|
|
.name = "count"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_read_v1E_01 = {
|
|
.name = "rpc_sim_read",
|
|
.header_length = NV_SIZEOF32(rpc_sim_read_v1E_01),
|
|
.fdesc = vmiopd_fdesc_t_rpc_sim_read_v1E_01
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_sim_write_v1E_01
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_write_v1E_01[] = {
|
|
{
|
|
.vtype = vtype_char_array,
|
|
.offset = NV_OFFSETOF(rpc_sim_write_v1E_01, path),
|
|
.array_length = 0x100,
|
|
.name = "path"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_sim_write_v1E_01, index),
|
|
.name = "index"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_sim_write_v1E_01, count),
|
|
.name = "count"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_sim_write_v1E_01, data),
|
|
.name = "data"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_write_v1E_01 = {
|
|
.name = "rpc_sim_write",
|
|
.header_length = NV_SIZEOF32(rpc_sim_write_v1E_01),
|
|
.fdesc = vmiopd_fdesc_t_rpc_sim_write_v1E_01
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_ucode_libos_print_v1E_08
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, ucodeEngDesc),
|
|
.name = "ucodeEngDesc"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBufSize),
|
|
.name = "libosPrintBufSize"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU8_array,
|
|
.offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBuf),
|
|
.array_length = 0,
|
|
.name = "libosPrintBuf"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ucode_libos_print_v1E_08 = {
|
|
.name = "rpc_ucode_libos_print",
|
|
.header_length = NV_SIZEOF32(rpc_ucode_libos_print_v1E_08),
|
|
.fdesc = vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_init_done_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_init_done_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_init_done_v17_00, not_used),
|
|
.name = "not_used"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_init_done_v17_00 = {
|
|
.name = "rpc_init_done",
|
|
.header_length = NV_SIZEOF32(rpc_init_done_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_init_done_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_semaphore_schedule_callback_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvU64,
|
|
.offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, GPUVA),
|
|
.name = "GPUVA"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hVASpace),
|
|
.name = "hVASpace"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, ReleaseValue),
|
|
.name = "ReleaseValue"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, Flags),
|
|
.name = "Flags"
|
|
},
|
|
{
|
|
.vtype = vtype_NvU32,
|
|
.offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, completionStatus),
|
|
.name = "completionStatus"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hClient),
|
|
.name = "hClient"
|
|
},
|
|
{
|
|
.vtype = vtype_NvHandle,
|
|
.offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hEvent),
|
|
.name = "hEvent"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00 = {
|
|
.name = "rpc_semaphore_schedule_callback",
|
|
.header_length = NV_SIZEOF32(rpc_semaphore_schedule_callback_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00,
|
|
.offset = NV_OFFSETOF(rpc_perf_gpu_boost_sync_limits_callback_v17_00, params),
|
|
.name = "params"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 = {
|
|
.name = "rpc_perf_gpu_boost_sync_limits_callback",
|
|
.header_length = NV_SIZEOF32(rpc_perf_gpu_boost_sync_limits_callback_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00
|
|
};
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_perf_bridgeless_info_update_v17_00
|
|
static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00[] = {
|
|
{
|
|
.vtype = vtype_NvU64,
|
|
.offset = NV_OFFSETOF(rpc_perf_bridgeless_info_update_v17_00, bBridgeless),
|
|
.name = "bBridgeless"
|
|
},
|
|
{
|
|
.vtype = vt_end
|
|
}
|
|
};
|
|
|
|
static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = {
|
|
.name = "rpc_perf_bridgeless_info_update",
|
|
.header_length = NV_SIZEOF32(rpc_perf_bridgeless_info_update_v17_00),
|
|
.fdesc = vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00
|
|
};
|
|
#endif
|
|
|
|
#endif
|
|
|
|
#ifdef RPC_DEBUG_PRINT_FUNCTIONS
|
|
// These are definitions for versioned functions. These will be used for RPC logging in the vmioplugin.
|
|
#define SDK_DEBUG_PRINT_FUNCTIONS
|
|
#include "g_sdk-structures.h"
|
|
#undef SDK_DEBUG_PRINT_FUNCTIONS
|
|
#ifndef SKIP_PRINT_rpc_nop_v03_00
|
|
vmiopd_mdesc_t *rpcdebugNop_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_nop_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00
|
|
vmiopd_mdesc_t *rpcdebugSetGuestSystemInfo_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_alloc_memory_v13_01
|
|
vmiopd_mdesc_t *rpcdebugAllocMemory_v13_01(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_alloc_memory_v13_01;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_free_v03_00
|
|
vmiopd_mdesc_t *rpcdebugFree_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_free_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00
|
|
vmiopd_mdesc_t *rpcdebugMapMemoryDma_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_map_memory_dma_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00
|
|
vmiopd_mdesc_t *rpcdebugUnmapMemoryDma_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_dup_object_v03_00
|
|
vmiopd_mdesc_t *rpcdebugDupObject_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_dup_object_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_idle_channels_v03_00
|
|
vmiopd_mdesc_t *rpcdebugIdleChannels_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_idle_channels_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v03_00
|
|
vmiopd_mdesc_t *rpcdebugUnloadingGuestDriver_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_unloading_guest_driver_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07
|
|
vmiopd_mdesc_t *rpcdebugUnloadingGuestDriver_v1F_07(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01
|
|
vmiopd_mdesc_t *rpcdebugGpuExecRegOps_v12_01(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05
|
|
vmiopd_mdesc_t *rpcdebugSetPageDirectory_v1E_05(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_set_page_directory_v1E_05;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_set_page_directory_v03_00
|
|
vmiopd_mdesc_t *rpcdebugSetPageDirectory_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_set_page_directory_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05
|
|
vmiopd_mdesc_t *rpcdebugUnsetPageDirectory_v1E_05(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_unset_page_directory_v03_00
|
|
vmiopd_mdesc_t *rpcdebugUnsetPageDirectory_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_unset_page_directory_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00
|
|
vmiopd_mdesc_t *rpcdebugGetGspStaticInfo_v14_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00
|
|
vmiopd_mdesc_t *rpcdebugUpdateBarPde_v15_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_update_bar_pde_v15_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00
|
|
vmiopd_mdesc_t *rpcdebugVgpuPfRegRead32_v15_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rmfs_init_v15_00
|
|
vmiopd_mdesc_t *rpcdebugRmfsInit_v15_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_rmfs_init_v15_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rmfs_close_queue_v15_00
|
|
vmiopd_mdesc_t *rpcdebugRmfsCloseQueue_v15_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_rmfs_close_queue_v15_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rmfs_cleanup_v15_00
|
|
vmiopd_mdesc_t *rpcdebugRmfsCleanup_v15_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_rmfs_cleanup_v15_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rmfs_test_v15_00
|
|
vmiopd_mdesc_t *rpcdebugRmfsTest_v15_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_rmfs_test_v15_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00
|
|
vmiopd_mdesc_t *rpcdebugGspSetSystemInfo_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_gsp_set_system_info_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_set_registry_v17_00
|
|
vmiopd_mdesc_t *rpcdebugSetRegistry_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_set_registry_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gsp_rm_alloc_v03_00
|
|
vmiopd_mdesc_t *rpcdebugGspRmAlloc_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_gsp_rm_alloc_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gsp_rm_control_v03_00
|
|
vmiopd_mdesc_t *rpcdebugGspRmControl_v03_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_gsp_rm_control_v03_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_dump_protobuf_component_v18_12
|
|
vmiopd_mdesc_t *rpcdebugDumpProtobufComponent_v18_12(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_dump_protobuf_component_v18_12;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_run_cpu_sequencer_v17_00
|
|
vmiopd_mdesc_t *rpcdebugRunCpuSequencer_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_run_cpu_sequencer_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_post_event_v17_00
|
|
vmiopd_mdesc_t *rpcdebugPostEvent_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_post_event_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rc_triggered_v17_02
|
|
vmiopd_mdesc_t *rpcdebugRcTriggered_v17_02(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_rc_triggered_v17_02;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_os_error_log_v17_00
|
|
vmiopd_mdesc_t *rpcdebugOsErrorLog_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_os_error_log_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_rg_line_intr_v17_00
|
|
vmiopd_mdesc_t *rpcdebugRgLineIntr_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_rg_line_intr_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_display_modeset_v01_00
|
|
vmiopd_mdesc_t *rpcdebugDisplayModeset_v01_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_display_modeset_v01_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v17_00
|
|
vmiopd_mdesc_t *rpcdebugGpuacctPerfmonUtilSamples_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_vgpu_gsp_plugin_triggered_v17_00
|
|
vmiopd_mdesc_t *rpcdebugVgpuGspPluginTriggered_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_vgpu_config_event_v17_00
|
|
vmiopd_mdesc_t *rpcdebugVgpuConfigEvent_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_vgpu_config_event_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_dce_rm_init_v01_00
|
|
vmiopd_mdesc_t *rpcdebugDceRmInit_v01_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_dce_rm_init_v01_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_sim_read_v1E_01
|
|
vmiopd_mdesc_t *rpcdebugSimRead_v1E_01(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_sim_read_v1E_01;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_sim_write_v1E_01
|
|
vmiopd_mdesc_t *rpcdebugSimWrite_v1E_01(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_sim_write_v1E_01;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_ucode_libos_print_v1E_08
|
|
vmiopd_mdesc_t *rpcdebugUcodeLibosPrint_v1E_08(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_ucode_libos_print_v1E_08;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_init_done_v17_00
|
|
vmiopd_mdesc_t *rpcdebugInitDone_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_init_done_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_semaphore_schedule_callback_v17_00
|
|
vmiopd_mdesc_t *rpcdebugSemaphoreScheduleCallback_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00
|
|
vmiopd_mdesc_t *rpcdebugPerfGpuBoostSyncLimitsCallback_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00;
|
|
}
|
|
#endif
|
|
|
|
#ifndef SKIP_PRINT_rpc_perf_bridgeless_info_update_v17_00
|
|
vmiopd_mdesc_t *rpcdebugPerfBridgelessInfoUpdate_v17_00(void)
|
|
{
|
|
return &vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00;
|
|
}
|
|
#endif
|
|
|
|
|
|
#endif
|
|
|
|
#ifdef RPC_GENERIC_UNION
|
|
// This is a generic union, that will be used for the communication between the vmioplugin & guest RM.
|
|
typedef union rpc_generic_union {
|
|
rpc_set_guest_system_info_v03_00 set_guest_system_info_v03_00;
|
|
rpc_set_guest_system_info_v set_guest_system_info_v;
|
|
rpc_alloc_memory_v13_01 alloc_memory_v13_01;
|
|
rpc_alloc_memory_v alloc_memory_v;
|
|
rpc_free_v03_00 free_v03_00;
|
|
rpc_free_v free_v;
|
|
rpc_map_memory_dma_v03_00 map_memory_dma_v03_00;
|
|
rpc_map_memory_dma_v map_memory_dma_v;
|
|
rpc_unmap_memory_dma_v03_00 unmap_memory_dma_v03_00;
|
|
rpc_unmap_memory_dma_v unmap_memory_dma_v;
|
|
rpc_dup_object_v03_00 dup_object_v03_00;
|
|
rpc_dup_object_v dup_object_v;
|
|
rpc_idle_channels_v03_00 idle_channels_v03_00;
|
|
rpc_idle_channels_v idle_channels_v;
|
|
rpc_unloading_guest_driver_v1F_07 unloading_guest_driver_v1F_07;
|
|
rpc_unloading_guest_driver_v unloading_guest_driver_v;
|
|
rpc_gpu_exec_reg_ops_v12_01 gpu_exec_reg_ops_v12_01;
|
|
rpc_gpu_exec_reg_ops_v gpu_exec_reg_ops_v;
|
|
rpc_set_page_directory_v1E_05 set_page_directory_v1E_05;
|
|
rpc_set_page_directory_v03_00 set_page_directory_v03_00;
|
|
rpc_set_page_directory_v set_page_directory_v;
|
|
rpc_unset_page_directory_v1E_05 unset_page_directory_v1E_05;
|
|
rpc_unset_page_directory_v03_00 unset_page_directory_v03_00;
|
|
rpc_unset_page_directory_v unset_page_directory_v;
|
|
rpc_get_gsp_static_info_v14_00 get_gsp_static_info_v14_00;
|
|
rpc_get_gsp_static_info_v get_gsp_static_info_v;
|
|
rpc_update_bar_pde_v15_00 update_bar_pde_v15_00;
|
|
rpc_update_bar_pde_v update_bar_pde_v;
|
|
rpc_vgpu_pf_reg_read32_v15_00 vgpu_pf_reg_read32_v15_00;
|
|
rpc_vgpu_pf_reg_read32_v vgpu_pf_reg_read32_v;
|
|
rpc_rmfs_init_v15_00 rmfs_init_v15_00;
|
|
rpc_rmfs_init_v rmfs_init_v;
|
|
rpc_rmfs_test_v15_00 rmfs_test_v15_00;
|
|
rpc_rmfs_test_v rmfs_test_v;
|
|
rpc_gsp_set_system_info_v17_00 gsp_set_system_info_v17_00;
|
|
rpc_gsp_set_system_info_v gsp_set_system_info_v;
|
|
rpc_gsp_rm_alloc_v03_00 gsp_rm_alloc_v03_00;
|
|
rpc_gsp_rm_alloc_v gsp_rm_alloc_v;
|
|
rpc_gsp_rm_control_v03_00 gsp_rm_control_v03_00;
|
|
rpc_gsp_rm_control_v gsp_rm_control_v;
|
|
rpc_dump_protobuf_component_v18_12 dump_protobuf_component_v18_12;
|
|
rpc_dump_protobuf_component_v dump_protobuf_component_v;
|
|
rpc_run_cpu_sequencer_v17_00 run_cpu_sequencer_v17_00;
|
|
rpc_run_cpu_sequencer_v run_cpu_sequencer_v;
|
|
rpc_post_event_v17_00 post_event_v17_00;
|
|
rpc_post_event_v post_event_v;
|
|
rpc_rc_triggered_v17_02 rc_triggered_v17_02;
|
|
rpc_rc_triggered_v rc_triggered_v;
|
|
rpc_os_error_log_v17_00 os_error_log_v17_00;
|
|
rpc_os_error_log_v os_error_log_v;
|
|
rpc_rg_line_intr_v17_00 rg_line_intr_v17_00;
|
|
rpc_rg_line_intr_v rg_line_intr_v;
|
|
rpc_display_modeset_v01_00 display_modeset_v01_00;
|
|
rpc_display_modeset_v display_modeset_v;
|
|
rpc_gpuacct_perfmon_util_samples_v17_00 gpuacct_perfmon_util_samples_v17_00;
|
|
rpc_gpuacct_perfmon_util_samples_v gpuacct_perfmon_util_samples_v;
|
|
rpc_vgpu_gsp_plugin_triggered_v17_00 vgpu_gsp_plugin_triggered_v17_00;
|
|
rpc_vgpu_gsp_plugin_triggered_v vgpu_gsp_plugin_triggered_v;
|
|
rpc_vgpu_config_event_v17_00 vgpu_config_event_v17_00;
|
|
rpc_vgpu_config_event_v vgpu_config_event_v;
|
|
rpc_dce_rm_init_v01_00 dce_rm_init_v01_00;
|
|
rpc_dce_rm_init_v dce_rm_init_v;
|
|
rpc_sim_read_v1E_01 sim_read_v1E_01;
|
|
rpc_sim_read_v sim_read_v;
|
|
rpc_sim_write_v1E_01 sim_write_v1E_01;
|
|
rpc_sim_write_v sim_write_v;
|
|
rpc_ucode_libos_print_v1E_08 ucode_libos_print_v1E_08;
|
|
rpc_ucode_libos_print_v ucode_libos_print_v;
|
|
rpc_init_done_v17_00 init_done_v17_00;
|
|
rpc_init_done_v init_done_v;
|
|
rpc_semaphore_schedule_callback_v17_00 semaphore_schedule_callback_v17_00;
|
|
rpc_semaphore_schedule_callback_v semaphore_schedule_callback_v;
|
|
rpc_perf_gpu_boost_sync_limits_callback_v17_00 perf_gpu_boost_sync_limits_callback_v17_00;
|
|
rpc_perf_gpu_boost_sync_limits_callback_v perf_gpu_boost_sync_limits_callback_v;
|
|
rpc_perf_bridgeless_info_update_v17_00 perf_bridgeless_info_update_v17_00;
|
|
rpc_perf_bridgeless_info_update_v perf_bridgeless_info_update_v;
|
|
} rpc_generic_union;
|
|
|
|
#endif
|
|
|
|
#ifdef RPC_UNION_MEMBER_NAME_FUNCTIONS_CMD
|
|
#define SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD
|
|
#include "g_sdk-structures.h"
|
|
#undef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD
|
|
|
|
#endif
|
|
|
|
|
|
#ifdef RPC_ARRAY_LENGTH_FUNCTIONS
|
|
#define SDK_ARRAY_LENGTH_FUNCTIONS
|
|
#include "g_sdk-structures.h"
|
|
#undef SDK_ARRAY_LENGTH_FUNCTIONS
|
|
|
|
// Array length functions for IDLE_CHANNELS:
|
|
static NV_STATUS get_array_length_rpc_idle_channels_v03_00_channel_list(void *msg, NvS32 bytes_remaining, uint32_t* length)
|
|
{
|
|
rpc_idle_channels_v03_00 *param = msg;
|
|
|
|
if ((NvS32)(NV_OFFSETOF(rpc_idle_channels_v03_00, nchannels) + sizeof(param->nchannels)) > bytes_remaining)
|
|
return NV_ERR_BUFFER_TOO_SMALL;
|
|
|
|
*length = param->nchannels;
|
|
return NV_OK;
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef AUTOGENERATE_RPC_MIN_SUPPORTED_VERSION_INFORMATION
|
|
#define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MAJOR 0x18
|
|
#define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MINOR 0x00
|
|
#endif
|