mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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362 lines
14 KiB
C
362 lines
14 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrl2080/ctrl2080mc.finn
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//
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#include "ctrl/ctrl2080/ctrl2080base.h"
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#include "nvcfg_sdk.h"
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/* NV20_SUBDEVICE_XX mc control commands and parameters */
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/**
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* NV2080_CTRL_CMD_MC_GET_ARCH_INFO
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*
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* This command returns chip architecture information from the
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* master control engine in the specified GPU.
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*
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* architecture
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* This parameter specifies the architecture level for the GPU.
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* implementation
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* This parameter specifies the implementation of the architecture
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* for the GPU.
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* revision
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* This parameter specifies the revision of the mask used to produce
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* the GPU.
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* subRevision
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* This parameter specific the sub revision of the GPU. Value is one of
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* NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_*
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV2080_CTRL_CMD_MC_GET_ARCH_INFO (0x20801701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID (0x1U)
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typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
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NvU32 architecture;
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NvU32 implementation;
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NvU32 revision;
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NvU8 subRevision;
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} NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS;
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/* valid architecture values */
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#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X (0xE0000023)
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#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 (0x00000160)
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#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170)
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#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 (0x00000180)
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#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 (0x00000190)
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#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 (0x000001A0)
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#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 (0x000001B0)
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/* valid ARCHITECTURE_T23X implementation values */
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 (0x00000004)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D (0x00000005)
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/* valid ARCHITECTURE_TU10x implementation values */
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 (0x00000000)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 (0x00000002)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 (0x00000004)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 (0x00000006)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 (0x00000008)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 (0x00000007)
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/* valid ARCHITECTURE_GA10x implementation values */
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 (0x00000000)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 (0x00000002)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 (0x00000003)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 (0x00000004)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 (0x00000006)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 (0x00000007)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B (0x0000000B)
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/* valid ARCHITECTURE_GH10x implementation values */
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 (0x00000000)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC (0x00000001)
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/* valid ARCHITECTURE_AD10x implementation values */
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 (0x00000000)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 (0x00000001)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 (0x00000001)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 (0x00000002)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 (0x00000003)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 (0x00000004)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 (0x00000006)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 (0x00000007)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B (0x0000000B)
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/* valid ARCHITECTURE_GB10x implementation values */
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 (0x00000000)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 (0x00000002)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB110 (0x00000003)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB112 (0x00000004)
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/* valid ARCHITECTURE_GB20x implementation values */
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 (0x00000000)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 (0x00000002)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 (0x00000003)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 (0x00000005)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 (0x00000006)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 (0x00000007)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20B (0x0000000B)
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#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20C (0x0000000C)
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/* Valid Chip sub revisions */
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#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)
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#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P (0x00000001)
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#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q (0x00000002)
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#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R (0x00000003)
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/*
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* NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS
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*
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* This command instructs the RM to service interrupts for the specified
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* engine(s).
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*
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* engines
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* This parameter specifies which engines should have their interrupts
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* serviced.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS (0x20801702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_MC_ENGINE_ID_GRAPHICS 0x00000001
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#define NV2080_CTRL_MC_ENGINE_ID_ALL 0xFFFFFFFF
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#define NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID (0x2U)
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typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS {
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NvU32 engines;
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} NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS;
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/*
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* NV2080_CTRL_CMD_MC_GET_MANUFACTURER
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*
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* This command returns the GPU manufacturer information for the associated
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* subdevice.
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*
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* manufacturer
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* This parameter returns the manufacturer value for the GPU.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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*/
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#define NV2080_CTRL_CMD_MC_GET_MANUFACTURER (0x20801703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID (0x3U)
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typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS {
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NvU32 manufacturer;
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} NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS;
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/*
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* NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP
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*
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* This call will setup RM to either service or ignore the
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* repayable fault interrupt.
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* This is a privileged call that can only be called by the UVM driver
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* when it will take ownership of the repalayable fault interrupt.
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*
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* Possible status values returned are:
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* NVOS_STATUS_SUCCESS
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* NVOS_STATUS_ERROR_INVALID_ARGUMENT
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* NVOS_STATUS_ERROR_NOT_SUPPORTED
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*/
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#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID (0xCU)
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typedef struct NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS {
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NvBool bOwnedByRm;
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} NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS;
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/*
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* NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS
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*
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* This command gets the notification interrupt vectors device for all VGPU engines from Host RM.
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*
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* Parameters:
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*
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* entries [out]
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* A buffer to store up to MAX_ENGINES entries of type
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* NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY.
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*
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* numEntries [out]
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* Number of populated entries in the provided buffer.
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS (0x2080170d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES 256
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typedef struct NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY {
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NvU32 nv2080EngineType;
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NvU32 notificationIntrVector;
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} NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY;
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#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID (0xDU)
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typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS {
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NvU32 numEntries;
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NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES];
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} NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS;
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/*
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* NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE
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*
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* This command gets the static interrupts needed by VGPU from Host RM.
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*
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* Parameters:
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*
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* entries [out]
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* A buffer to store up to MAX_ENGINES entries of type
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* NV2080_CTRL_MC_STATIC_INTR_ENTRY.
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*
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* numEntries [out]
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* Number of populated entries in the provided buffer.
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE (0x2080170e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX 32
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// Interface defines for static MC_ENGINE_IDX defines
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#define NV2080_INTR_TYPE_NULL (0x00000000)
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#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT (0x00000001)
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#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR (0x00000002)
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#define NV2080_INTR_TYPE_INFO_FAULT (0x00000003)
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#define NV2080_INTR_TYPE_REPLAYABLE_FAULT (0x00000004)
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#define NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR (0x00000005)
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#define NV2080_INTR_TYPE_ACCESS_CNTR (0x00000006)
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#define NV2080_INTR_TYPE_TMR (0x00000007)
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#define NV2080_INTR_TYPE_CPU_DOORBELL (0x00000008)
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#define NV2080_INTR_TYPE_GR0_FECS_LOG (0x00000009)
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#define NV2080_INTR_TYPE_GR1_FECS_LOG (0x0000000A)
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#define NV2080_INTR_TYPE_GR2_FECS_LOG (0x0000000B)
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#define NV2080_INTR_TYPE_GR3_FECS_LOG (0x0000000C)
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#define NV2080_INTR_TYPE_GR4_FECS_LOG (0x0000000D)
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#define NV2080_INTR_TYPE_GR5_FECS_LOG (0x0000000E)
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#define NV2080_INTR_TYPE_GR6_FECS_LOG (0x0000000F)
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#define NV2080_INTR_TYPE_GR7_FECS_LOG (0x00000010)
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typedef struct NV2080_CTRL_MC_STATIC_INTR_ENTRY {
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NvU32 nv2080IntrType;
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NvU32 pmcIntrMask;
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NvU32 intrVectorStall;
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NvU32 intrVectorNonStall;
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} NV2080_CTRL_MC_STATIC_INTR_ENTRY;
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#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID (0xEU)
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typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS {
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NvU32 numEntries;
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NV2080_CTRL_MC_STATIC_INTR_ENTRY entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX];
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} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS;
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/*!
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* Categories of interrupts.
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*
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* Each of these categories get a separate range of interrupt subtrees (top
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* level bits) corresponding to a set of interrupt leaves.
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* Interrupt leaves may overlap between two or more categories.
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* Interrupt leaves may or may not be contiguous.
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*/
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typedef enum NV2080_INTR_CATEGORY {
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NV2080_INTR_CATEGORY_DEFAULT = 0,
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NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
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NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
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NV2080_INTR_CATEGORY_RUNLIST = 3,
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NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
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NV2080_INTR_CATEGORY_UVM_OWNED = 5,
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NV2080_INTR_CATEGORY_UVM_SHARED = 6,
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NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
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} NV2080_INTR_CATEGORY;
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#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX
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typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
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// Maximum possible 64 subtrees, but 16 is enough for any existing silicon.
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NV_DECLARE_ALIGNED(NvU64 subtreeMask, 8);
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} NV2080_INTR_CATEGORY_SUBTREE_MAP;
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/*
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* NV2080_CTRL_CMD_MC_GET_INTR_CATEGORY_SUBTREE_MAP
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*
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* This command gets a mapping from every interrupt category -> subtrees used from
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* Host RM.
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*/
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#define NV2080_CTRL_CMD_MC_GET_INTR_CATEGORY_SUBTREE_MAP (0x2080170f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS_MESSAGE_ID (0xFU)
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typedef struct NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS {
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NV_DECLARE_ALIGNED(NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT], 8);
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} NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS;
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/* _ctrl2080mc_h_ */
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