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94 lines
3.6 KiB
C
94 lines
3.6 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrlc370/ctrlc370or.finn
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//
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#include "ctrl/ctrlc370/ctrlc370base.h"
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/* C370 is partially derived from 5070 */
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#include "ctrl/ctrl5070/ctrl5070or.h"
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//
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// NVC370_CTRL_CMD_SET_SOR_FLUSH_MODE
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//
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// This command is used enable/disable flush mode on all the heads attached to the SOR
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// Applies to NV Display 5.0+ (GB20X+ and T264+)
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// [in] subDeviceInstance
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// This parameter specifies the subdevice instance within the
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// NV04_DISPLAY_COMMON parent device to which the operation should be
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// directed. This parameter must specify a value between zero and the
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// total number of subdevices within the parent device. This parameter
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// should be set to zero for default behavior.
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// [in] sorNumber
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// All heads connected to this SOR will be programmed
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// [in] headIndex
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// Phase 1 flush exit programs SF_DP_LINKCTL for each head separately
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// [in] attachFailedHeadMask
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// Head mask for the heads where add stream failed
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// [in] phase
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// Flush has 2 Phases (Broad overview):
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// - For Entry
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// - Phase 1: Set core to debug, disable AUDIO and HDCP and engage flush
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// - Phase 2: Disable SOR and SF
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// - For Exit
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// - Phase 1: Program SF for each stream
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// - Phase 2: Exit flush, enable AUDIO and HDCP and disengage flush
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// This design allows interleaving add/delete MST information in-between them
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// [in] bEnable
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// Whether to enable/disable flush
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// Possible return values:
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// NV_OK
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// NV_ERR_NOT_SUPPORTED
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//
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#define NVC370_CTRL_CMD_SET_SOR_FLUSH_MODE (0xc3700401U) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_OR_INTERFACE_ID << 8) | NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID" */
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#define NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID (0x1U)
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typedef struct NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS {
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NvU32 subDeviceInstance;
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NvU32 sorNumber;
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NvU32 headIndex;
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NvU32 attachFailedHeadMask;
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NvU8 phase;
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NvBool bEnable;
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} NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS;
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/* _ctrlc370or_h_ */
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#define NVC370_CTRL_SET_SOR_FLUSH_RUN 1:0
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#define NVC370_CTRL_SET_SOR_FLUSH_RUN_PHASE_INVALID (0x00000000U)
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#define NVC370_CTRL_SET_SOR_FLUSH_RUN_PHASE1 (0x00000001U)
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#define NVC370_CTRL_SET_SOR_FLUSH_RUN_PHASE2 (0x00000002U)
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