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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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181 lines
8.0 KiB
C
181 lines
8.0 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrl2080/ctrl2080dma.finn
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//
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#include "ctrl/ctrl2080/ctrl2080base.h"
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/* NV20_SUBDEVICE_XX dma control commands and parameters */
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/*
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* NV2080_CTRL_CMD_DMA_INVALIDATE_TLB
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*
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* This command invalidates the GPU TLB. This is intended to be used
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* by RM clients that manage their own TLB consistency when updating
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* page tables on their own, or with DEFER_TLB_INVALIDATION options
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* to other RM APIs.
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*
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* hVASpace
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* This parameter specifies the VASpace object whose MMU TLB entries needs to be invalidated.
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* Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace.
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* Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC.
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*
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* This call can be used with the NV50_DEFERRED_API_CLASS (class 0x5080).
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*
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* Possible status values returned are:
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* NV_OK
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* NVOS_STATUS_TIMEOUT_RETRY
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* NV_ERR_NOT_SUPPORTED
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*/
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#define NV2080_CTRL_CMD_DMA_INVALIDATE_TLB (0x20802502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0x2U)
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typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
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NvHandle hClient; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
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NvHandle hDevice; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
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NvU32 engine; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
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NvHandle hVASpace;
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} NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS;
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS 0:0
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO 1:1
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY 2:2
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE 3:3
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB 4:4
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV 5:5
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG 6:6
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD 7:7
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION 8:8
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON 9:9
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS 10:10
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE (0x00000001)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR 11:11
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE (0x00000000)
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#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE (0x00000001)
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/*
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* NV2080_CTRL_DMA_INFO
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*
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* This structure represents a single 32bit dma engine value. Clients
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* request a particular DMA engine value by specifying a unique dma
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* information index.
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*
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* Legal dma information index values are:
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* NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
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* This index can be used to request the system address size in bits.
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*/
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typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_DMA_INFO;
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/* valid dma info index values */
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#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000)
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/* set INDEX_MAX to greatest possible index value */
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#define NV2080_CTRL_DMA_INFO_INDEX_MAX NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
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/*
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* NV2080_CTRL_CMD_DMA_GET_INFO
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*
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* This command returns dma engine information for the associated GPU.
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* Requests to retrieve dma information use an array of one or more
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* NV2080_CTRL_DMA_INFO structures.
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*
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* dmaInfoTblSize
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* This field specifies the number of valid entries in the dmaInfoList
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* array. This value cannot exceed NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES.
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* dmaInfoTbl
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* This parameter contains the client's dma info table into
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* which the dma info values will be transferred by the RM.
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* The dma info table is an array of NV2080_CTRL_DMA_INFO structures.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV2080_CTRL_CMD_DMA_GET_INFO (0x20802503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID" */
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/* maximum number of NV2080_CTRL_DMA_INFO entries per request */
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#define NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES (256)
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#define NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID (0x3U)
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typedef struct NV2080_CTRL_DMA_GET_INFO_PARAMS {
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NvU32 dmaInfoTblSize;
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/*
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* C form:
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* NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
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*/
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NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
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} NV2080_CTRL_DMA_GET_INFO_PARAMS;
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typedef struct NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO {
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/*!
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* 64KB aligned address of source 64KB tile for comptag reswizzle.
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*/
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NvU32 srcAddr;
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/*!
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* 64KB aligned address of destination 64KB tile for comptag reswizzle.
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*/
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NvU32 dstAddr;
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/*!
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* Comptag index assigned to the 64K sized tile relative to
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* the compcacheline. Absolute comptag index would be:
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* startComptagIndex + relComptagIndex.
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*/
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NvU16 relComptagIndex;
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} NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO;
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// _ctrl2080dma_h_
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