mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-03 23:09:23 +00:00
769 lines
17 KiB
C
769 lines
17 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "flcn/haldefs_flcn_nvswitch.h"
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#include "flcn/flcn_nvswitch.h"
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#include "rmflcncmdif_nvswitch.h"
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#include "flcnifcmn.h"
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typedef union RM_FLCN_CMD RM_FLCN_CMD, *PRM_FLCN_CMD;
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typedef union RM_FLCN_MSG RM_FLCN_MSG, *PRM_FLCN_MSG;
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// OBJECT Interfaces
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NV_STATUS
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flcnQueueReadData
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 queueId,
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void *pData,
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NvBool bMsg
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueReadData != (void *)0);
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return pFlcn->pHal->queueReadData(device, pFlcn, queueId, pData, bMsg);
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}
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NV_STATUS
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flcnQueueCmdWrite
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 queueId,
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RM_FLCN_CMD *pCmd,
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NVSWITCH_TIMEOUT *pTimeout
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueCmdWrite != (void *)0);
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return pFlcn->pHal->queueCmdWrite(device, pFlcn, queueId, pCmd, pTimeout);
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}
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NV_STATUS
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flcnQueueCmdCancel
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 seqDesc
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueCmdCancel != (void *)0);
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return pFlcn->pHal->queueCmdCancel(device, pFlcn, seqDesc);
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}
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NV_STATUS
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flcnQueueCmdPostNonBlocking
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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PRM_FLCN_CMD pCmd,
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PRM_FLCN_MSG pMsg,
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void *pPayload,
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NvU32 queueIdLogical,
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FlcnQMgrClientCallback pCallback,
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void *pCallbackParams,
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NvU32 *pSeqDesc,
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NVSWITCH_TIMEOUT *pTimeout
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueCmdPostNonBlocking != (void *)0);
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return pFlcn->pHal->queueCmdPostNonBlocking(device, pFlcn, pCmd, pMsg, pPayload, queueIdLogical, pCallback, pCallbackParams, pSeqDesc, pTimeout);
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}
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NV_STATUS
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flcnQueueCmdPostBlocking
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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PRM_FLCN_CMD pCmd,
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PRM_FLCN_MSG pMsg,
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void *pPayload,
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NvU32 queueIdLogical,
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NvU32 *pSeqDesc,
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NVSWITCH_TIMEOUT *pTimeout
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)
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{
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NV_STATUS status;
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status = flcnQueueCmdPostNonBlocking(device, pFlcn, pCmd, pMsg, pPayload,
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queueIdLogical, NULL, NULL, pSeqDesc, pTimeout);
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if (status != NV_OK)
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{
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NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
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"Failed to post command to SOE. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n",
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pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags,
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pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd);
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return status;
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}
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status = flcnQueueCmdWait(device, pFlcn, *pSeqDesc, pTimeout);
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if (status == NV_ERR_TIMEOUT)
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{
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NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_TIMEOUT,
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"Timed out while waiting for SOE command completion. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n",
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pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags,
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pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd);
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flcnQueueCmdCancel(device, pFlcn, *pSeqDesc);
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}
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return status;
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}
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NV_STATUS
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flcnQueueCmdWait
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 seqDesc,
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NVSWITCH_TIMEOUT *pTimeout
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueCmdWait != (void *)0);
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return pFlcn->pHal->queueCmdWait(device, pFlcn, seqDesc, pTimeout);
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}
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NvU8
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flcnCoreRevisionGet
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(
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struct nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->coreRevisionGet != (void *)0);
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return pFlcn->pHal->coreRevisionGet(device, pFlcn);
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}
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void
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flcnMarkNotReady
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->markNotReady != (void *)0);
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pFlcn->pHal->markNotReady(device, pFlcn);
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}
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NV_STATUS
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flcnCmdQueueHeadGet
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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FLCNQUEUE *pQueue,
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NvU32 *pHead
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->cmdQueueHeadGet != (void *)0);
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return pFlcn->pHal->cmdQueueHeadGet(device, pFlcn, pQueue, pHead);
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}
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NV_STATUS
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flcnMsgQueueHeadGet
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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FLCNQUEUE *pQueue,
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NvU32 *pHead
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->msgQueueHeadGet != (void *)0);
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return pFlcn->pHal->msgQueueHeadGet(device, pFlcn, pQueue, pHead);
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}
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NV_STATUS
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flcnCmdQueueTailGet
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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FLCNQUEUE *pQueue,
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NvU32 *pTail
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->cmdQueueTailGet != (void *)0);
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return pFlcn->pHal->cmdQueueTailGet(device, pFlcn, pQueue, pTail);
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}
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NV_STATUS
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flcnMsgQueueTailGet
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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FLCNQUEUE *pQueue,
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NvU32 *pTail
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->msgQueueTailGet != (void *)0);
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return pFlcn->pHal->msgQueueTailGet(device, pFlcn, pQueue, pTail);
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}
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NV_STATUS
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flcnCmdQueueHeadSet
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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FLCNQUEUE *pQueue,
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NvU32 head
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->cmdQueueHeadSet != (void *)0);
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return pFlcn->pHal->cmdQueueHeadSet(device, pFlcn, pQueue, head);
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}
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NV_STATUS
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flcnMsgQueueHeadSet
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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FLCNQUEUE *pQueue,
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NvU32 head
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->msgQueueHeadSet != (void *)0);
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return pFlcn->pHal->msgQueueHeadSet(device, pFlcn, pQueue, head);
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}
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NV_STATUS
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flcnCmdQueueTailSet
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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FLCNQUEUE *pQueue,
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NvU32 tail
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->cmdQueueTailSet != (void *)0);
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return pFlcn->pHal->cmdQueueTailSet(device, pFlcn, pQueue, tail);
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}
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NV_STATUS
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flcnMsgQueueTailSet
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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FLCNQUEUE *pQueue,
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NvU32 tail
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->msgQueueTailSet != (void *)0);
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return pFlcn->pHal->msgQueueTailSet(device, pFlcn, pQueue, tail);
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}
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PFLCN_QMGR_SEQ_INFO
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flcnQueueSeqInfoFind
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 seqDesc
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueSeqInfoFind != (void *)0);
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return pFlcn->pHal->queueSeqInfoFind(device, pFlcn, seqDesc);
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}
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PFLCN_QMGR_SEQ_INFO
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flcnQueueSeqInfoAcq
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueSeqInfoAcq != (void *)0);
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return pFlcn->pHal->queueSeqInfoAcq(device, pFlcn);
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}
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void
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flcnQueueSeqInfoRel
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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PFLCN_QMGR_SEQ_INFO pSeqInfo
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueSeqInfoRel != (void *)0);
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pFlcn->pHal->queueSeqInfoRel(device, pFlcn, pSeqInfo);
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}
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void
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flcnQueueSeqInfoStateInit
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueSeqInfoStateInit != (void *)0);
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pFlcn->pHal->queueSeqInfoStateInit(device, pFlcn);
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}
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void
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flcnQueueSeqInfoCancelAll
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueSeqInfoCancelAll != (void *)0);
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pFlcn->pHal->queueSeqInfoCancelAll(device, pFlcn);
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}
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NV_STATUS
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flcnQueueSeqInfoFree
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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PFLCN_QMGR_SEQ_INFO pSeqInfo
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueSeqInfoFree != (void *)0);
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return pFlcn->pHal->queueSeqInfoFree(device, pFlcn, pSeqInfo);
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}
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NV_STATUS
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flcnQueueEventRegister
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 unitId,
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NvU8 *pMsg,
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FlcnQMgrClientCallback pCallback,
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void *pParams,
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NvU32 *pEvtDesc
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueEventRegister != (void *)0);
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return pFlcn->pHal->queueEventRegister(device, pFlcn, unitId, pMsg, pCallback, pParams, pEvtDesc);
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}
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NV_STATUS
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flcnQueueEventUnregister
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 evtDesc
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueEventUnregister != (void *)0);
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return pFlcn->pHal->queueEventUnregister(device, pFlcn, evtDesc);
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}
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NV_STATUS
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flcnQueueEventHandle
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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RM_FLCN_MSG *pMsg,
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NV_STATUS evtStatus
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueEventHandle != (void *)0);
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return pFlcn->pHal->queueEventHandle(device, pFlcn, pMsg, evtStatus);
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}
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NV_STATUS
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flcnQueueResponseHandle
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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RM_FLCN_MSG *pMsg
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueResponseHandle != (void *)0);
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return pFlcn->pHal->queueResponseHandle(device, pFlcn, pMsg);
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}
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NvU32
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flcnQueueCmdStatus
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 seqDesc
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->queueCmdStatus != (void *)0);
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return pFlcn->pHal->queueCmdStatus(device, pFlcn, seqDesc);
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}
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NV_STATUS
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flcnDmemCopyFrom
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 src,
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NvU8 *pDst,
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NvU32 sizeBytes,
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NvU8 port
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->dmemCopyFrom != (void *)0);
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return pFlcn->pHal->dmemCopyFrom(device, pFlcn, src, pDst, sizeBytes, port);
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}
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NV_STATUS
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flcnDmemCopyTo
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 dst,
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NvU8 *pSrc,
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NvU32 sizeBytes,
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NvU8 port
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)
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{
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NVSWITCH_ASSERT(pFlcn->pHal->dmemCopyTo != (void *)0);
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return pFlcn->pHal->dmemCopyTo(device, pFlcn, dst, pSrc, sizeBytes, port);
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}
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void
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flcnPostDiscoveryInit
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(
|
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nvswitch_device *device,
|
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PFLCN pFlcn
|
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)
|
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{
|
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NVSWITCH_ASSERT(pFlcn->pHal->postDiscoveryInit != (void *)0);
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pFlcn->pHal->postDiscoveryInit(device, pFlcn);
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}
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|
|
void
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flcnDbgInfoDmemOffsetSet
|
|
(
|
|
nvswitch_device *device,
|
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PFLCN pFlcn,
|
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NvU16 debugInfoDmemOffset
|
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)
|
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{
|
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NVSWITCH_ASSERT(pFlcn->pHal->dbgInfoDmemOffsetSet != (void *)0);
|
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pFlcn->pHal->dbgInfoDmemOffsetSet(device, pFlcn, debugInfoDmemOffset);
|
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}
|
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|
|
|
|
|
|
// HAL Interfaces
|
|
NV_STATUS
|
|
flcnConstruct_HAL
|
|
(
|
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nvswitch_device *device,
|
|
PFLCN pFlcn
|
|
)
|
|
{
|
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NVSWITCH_ASSERT(pFlcn->pHal->construct != (void *)0);
|
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return pFlcn->pHal->construct(device, pFlcn);
|
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}
|
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|
|
void
|
|
flcnDestruct_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->destruct != (void *)0);
|
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pFlcn->pHal->destruct(device, pFlcn);
|
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}
|
|
|
|
NvU32
|
|
flcnRegRead_HAL
|
|
(
|
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struct nvswitch_device *device,
|
|
PFLCN pFlcn,
|
|
NvU32 offset
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->regRead != (void *)0);
|
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return pFlcn->pHal->regRead(device, pFlcn, offset);
|
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}
|
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|
|
void
|
|
flcnRegWrite_HAL
|
|
(
|
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struct nvswitch_device *device,
|
|
PFLCN pFlcn,
|
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NvU32 offset,
|
|
NvU32 data
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->regWrite != (void *)0);
|
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pFlcn->pHal->regWrite(device, pFlcn, offset, data);
|
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}
|
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|
|
const char *
|
|
flcnGetName_HAL
|
|
(
|
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struct nvswitch_device *device,
|
|
PFLCN pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->getName != (void *)0);
|
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return pFlcn->pHal->getName(device, pFlcn);
|
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}
|
|
|
|
NvU8
|
|
flcnReadCoreRev_HAL
|
|
(
|
|
struct nvswitch_device *device,
|
|
PFLCN pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->readCoreRev != (void *)0);
|
|
return pFlcn->pHal->readCoreRev(device, pFlcn);
|
|
}
|
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|
|
void
|
|
flcnGetCoreInfo_HAL
|
|
(
|
|
struct nvswitch_device *device,
|
|
PFLCN pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->getCoreInfo != (void *)0);
|
|
pFlcn->pHal->getCoreInfo(device, pFlcn);
|
|
}
|
|
|
|
NV_STATUS
|
|
flcnDmemTransfer_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn,
|
|
NvU32 src,
|
|
NvU8 *pDst,
|
|
NvU32 sizeBytes,
|
|
NvU8 port,
|
|
NvBool bCopyFrom
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->dmemTransfer != (void *)0);
|
|
return pFlcn->pHal->dmemTransfer(device, pFlcn, src, pDst, sizeBytes, port, bCopyFrom);
|
|
}
|
|
|
|
void
|
|
flcnIntrRetrigger_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
FLCN *pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->intrRetrigger != (void *)0);
|
|
pFlcn->pHal->intrRetrigger(device, pFlcn);
|
|
}
|
|
|
|
NvBool
|
|
flcnAreEngDescsInitialized_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
FLCN *pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->areEngDescsInitialized != (void *)0);
|
|
return pFlcn->pHal->areEngDescsInitialized(device, pFlcn);
|
|
}
|
|
|
|
NV_STATUS
|
|
flcnWaitForResetToFinish_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
FLCN *pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->waitForResetToFinish != (void *)0);
|
|
return pFlcn->pHal->waitForResetToFinish(device, pFlcn);
|
|
}
|
|
|
|
void
|
|
flcnDbgInfoCapturePcTrace_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn
|
|
)
|
|
{
|
|
if (pFlcn->pHal->dbgInfoCapturePcTrace == (void *)0)
|
|
{
|
|
NVSWITCH_ASSERT(0);
|
|
return;
|
|
}
|
|
|
|
pFlcn->pHal->dbgInfoCapturePcTrace(device, pFlcn);
|
|
}
|
|
|
|
void
|
|
flcnDbgInfoCaptureRiscvPcTrace_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn
|
|
)
|
|
{
|
|
if (pFlcn->pHal->dbgInfoCaptureRiscvPcTrace == (void *)0)
|
|
{
|
|
NVSWITCH_ASSERT(0);
|
|
return;
|
|
}
|
|
|
|
pFlcn->pHal->dbgInfoCaptureRiscvPcTrace(device, pFlcn);
|
|
}
|
|
|
|
|
|
NvU32
|
|
flcnDmemSize_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn
|
|
)
|
|
{
|
|
if (pFlcn->pHal->dmemSize == (void *)0)
|
|
{
|
|
NVSWITCH_ASSERT(0);
|
|
return 0;
|
|
}
|
|
|
|
return pFlcn->pHal->dmemSize(device, pFlcn);
|
|
}
|
|
|
|
NvU32
|
|
flcnSetImemAddr_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn,
|
|
NvU32 dst
|
|
)
|
|
{
|
|
if (pFlcn->pHal->setImemAddr == (void *)0)
|
|
{
|
|
NVSWITCH_ASSERT(0);
|
|
return 0;
|
|
}
|
|
|
|
return pFlcn->pHal->setImemAddr(device, pFlcn, dst);
|
|
}
|
|
|
|
void
|
|
flcnImemCopyTo_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn,
|
|
NvU32 dst,
|
|
NvU8 *pSrc,
|
|
NvU32 sizeBytes,
|
|
NvBool bSecure,
|
|
NvU32 tag,
|
|
NvU8 port
|
|
)
|
|
{
|
|
if (pFlcn->pHal->imemCopyTo == (void *)0)
|
|
{
|
|
NVSWITCH_ASSERT(0);
|
|
return;
|
|
}
|
|
|
|
pFlcn->pHal->imemCopyTo(device, pFlcn, dst, pSrc, sizeBytes, bSecure, tag, port);
|
|
}
|
|
|
|
NvU32
|
|
flcnSetDmemAddr_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn,
|
|
NvU32 dst
|
|
)
|
|
{
|
|
if (pFlcn->pHal->setDmemAddr == (void *)0)
|
|
{
|
|
NVSWITCH_ASSERT(0);
|
|
return 0;
|
|
}
|
|
|
|
return pFlcn->pHal->setDmemAddr(device, pFlcn, dst);
|
|
}
|
|
|
|
NvU32
|
|
flcnRiscvRegRead_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn,
|
|
NvU32 offset
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->riscvRegRead != (void *)0);
|
|
return pFlcn->pHal->riscvRegRead(device, pFlcn, offset);
|
|
}
|
|
|
|
void
|
|
flcnRiscvRegWrite_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn,
|
|
NvU32 offset,
|
|
NvU32 data
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->riscvRegWrite != (void *)0);
|
|
pFlcn->pHal->riscvRegWrite(device, pFlcn, offset, data);
|
|
}
|
|
|
|
NV_STATUS
|
|
flcnDebugBufferInit_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
PFLCN pFlcn,
|
|
NvU32 debugBufferMaxSize,
|
|
NvU32 writeRegAddr,
|
|
NvU32 readRegAddr
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->debugBufferInit != (void *)0);
|
|
return pFlcn->pHal->debugBufferInit(device, pFlcn, debugBufferMaxSize, writeRegAddr, readRegAddr);
|
|
}
|
|
|
|
NV_STATUS
|
|
flcnDebugBufferDestroy_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
FLCN *pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->debugBufferDestroy != (void *)0);
|
|
return pFlcn->pHal->debugBufferDestroy(device, pFlcn);
|
|
}
|
|
|
|
NV_STATUS
|
|
flcnDebugBufferDisplay_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
FLCN *pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->debugBufferDisplay != (void *)0);
|
|
return pFlcn->pHal->debugBufferDisplay(device, pFlcn);
|
|
}
|
|
|
|
NvBool
|
|
flcnDebugBufferIsEmpty_HAL
|
|
(
|
|
nvswitch_device *device,
|
|
FLCN *pFlcn
|
|
)
|
|
{
|
|
NVSWITCH_ASSERT(pFlcn->pHal->debugBufferIsEmpty != (void *)0);
|
|
return pFlcn->pHal->debugBufferIsEmpty(device, pFlcn);
|
|
}
|
|
|