mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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426 lines
17 KiB
C
426 lines
17 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrlcb33.finn
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//
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#include "nvcfg_sdk.h"
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#include "ctrl/ctrlxxxx.h"
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/* NV_CONF_COMPUTE control commands and parameters */
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#define NV_CONF_COMPUTE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xCB33, NVCB33_CTRL_##cat, idx)
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#define NVCB33_CTRL_RESERVED (0x00)
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#define NVCB33_CTRL_CONF_COMPUTE (0x01)
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_NULL
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*
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* This command does nothing.
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* This command does not take any parameters.
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*
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* Possible return values:
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* NV_OK
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_NULL (0xcb330000) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID << 8) | 0x0" */
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES
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* This control call returns overall system and gpu capabilities
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*
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* Final operating environment depends on a lot of factors:
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* APM: Ampere Protected Memory
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* HCC: Hopper Confidential Compute
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* ---------------------------------------------------------------------------
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* SrNo CPU TEE GPU TEE GPU Platform GPU mode SW Status System Env
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* ---------------------------------------------------------------------------
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* 1 AMD SEV APM/HCC Silicon Production Production Production
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* 2 AMD SEV APM/HCC Silicon Production Development Simulation
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* 3 <Any> APM/HCC <Any> Debug <Any> Simulation
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* 4 Non SEV APM/HCC <Any> <Any> <Any> Simulation
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* 5 <Any> APM/HCC FMOD/EMU/RTL <Any> <Any> Simulation
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* ---------------------------------------------------------------------------
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*
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* Prameters:
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* cpuCapability: [OUT]
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* This indicates if cpu is capable of AMD SEV
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* gpusCapability: [OUT]
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* This indicates if all gpus in the system support APM/HCC.
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* This field doesn't mean APM/HCC is enabled.
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* environment: [OUT]
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* System environment can be production or simulation
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* ccFeature: [OUT]
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* Specifies if all gpus in the system have APM/HCC feature enabled
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* CC feature can be enabled/disabled using this control call:
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* NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_CC_FEATURE
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* devToolsMode: [OUT]
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* Dev tools mode is used for debugging/profiling
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* Dev tools mode is set at system level and implies that all GPUs in
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* the system have this mode enabled/disabled
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* multiGpuMode: [OUT]
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* Specifies the mode in which a multi gpu system is operating
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*
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* cpuCapability, gpusCapability & environment are determined by the
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* driver and cannot be modified later on
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES (0xcb330101) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x1" */
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#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0
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#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1
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#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2
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#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP 3
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#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM 4
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#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0
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#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1
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#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC 2
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#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE 0
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#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM 1
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#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD 2
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#define NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED 0
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#define NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED 1
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#define NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED 2
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#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED 0
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#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED 1
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#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE 0
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#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE 1
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#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NVLE 2
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS {
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NvU8 cpuCapability;
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NvU8 gpusCapability;
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NvU8 environment;
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NvU8 ccFeature;
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NvU8 devToolsMode;
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NvU8 multiGpuMode;
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} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS;
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE
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* This control call can be used to determine if all GPUs are ready to accept
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* work form clients.
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*
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* bAcceptClientRequest: [OUT]
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* NV_TRUE: all gpus accepting client work requests
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* NV_FALSE: all gpus blocking client work requests
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE (0xcb330104) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x4" */
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS {
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NvBool bAcceptClientRequest;
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} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS;
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE
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* This control call can be used to set gpu state to accept client requests
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* or to block client requests
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* This is a PRIVILEGED control call and can be set via admin tools
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*
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* bAcceptClientRequest:[IN]
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* NV_TRUE: set all gpus state to accept client work requests
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* NV_FALSE: set all gpus state to block client work requests
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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* NV_ERR_INSUFFICIENT_PERMISSIONS
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE (0xcb330105) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x5" */
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS {
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NvBool bAcceptClientRequest;
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} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS;
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE
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* This control call returns protected and unprotected vidmem size
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*
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* hSubDevice: [IN]
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* subdevice handle for the gpu whose vidmem size is requested
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* protectedMemSizeInKb: [OUT]
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* total protected memory size in kB
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* unprotectedMemSizeInKb: [OUT]
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* total unprotected memory size in kB
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE (0xcb330106) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x6" */
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS {
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NvHandle hSubDevice;
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NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8);
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NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8);
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} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS;
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE
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* This control call updates protected and unprotected vidmem size.
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* All memory is protected if APM/HCC is enabled. User can override
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* unprotectedMemSizeInKb and that will adjust protectedMemSizeInKb accordingly.
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* This is a PRIVILEGED control call and can be set via tools like nvidia-smi.
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* Vidmem size can be updated after driver load and before any client FB
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* allocations are made.
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*
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* hSubDevice: [IN]
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* subdevice handle for the gpu whose vidmem size is requested
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* protectedMemSizeInKb: [OUT]
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* total protected memory size in kB
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* unprotectedMemSizeInKb: [IN/OUT]
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* total unprotected memory size in kB
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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* NV_ERR_INSUFFICIENT_PERMISSIONS
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE (0xcb330107) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x7" */
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS {
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NvHandle hSubDevice;
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NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8);
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NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8);
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} NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS;
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS
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* This control call returns the max number of AES capable channels SEC2 and CE support.
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*
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* hSubDevice: [IN]
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* subdevice handle for the GPU queried
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* numSupportedSec2CCSecureChannels: [OUT]
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* Max number of AES capable channels SEC2 supports
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* numSupportedCeCCSecureChannels: [OUT]
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* Max number of channels CE supports with encrypt/decrypt
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS (0xcb330108) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x8" */
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#define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0x8U)
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS {
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NvHandle hSubDevice;
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NvU32 numSupportedSec2CCSecureChannels;
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NvU32 numSupportedCeCCSecureChannels;
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} NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS;
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE
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* This control call returns the GPU session certificate for the specified GPU.
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* The certificate size is the maximum of the certificate size of APM and CC.
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*
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* hSubDevice: [IN]
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* Subdevice handle for the GPU queried
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* certChain: [OUT]
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* Certificate chain for the GPU queried
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* certChainSize: [OUT]
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* Actual size of certChain data
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* attestationCertChain: [OUT]
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* Attestation certificate chain for the GPU queried
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* attestationCertChainSize: [OUT]
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* Actual size of attestationCertChain data
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE (0xcb330109) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x9" */
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#define NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE 0x1000
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#define NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE 0x1400
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#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID (0x9U)
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS {
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NvHandle hSubDevice;
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NvU8 certChain[NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE];
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NvU32 certChainSize;
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NvU8 attestationCertChain[NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE];
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NvU32 attestationCertChainSize;
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} NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS;
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION
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* This control call returns the GPU attestation report for the specified GPU.
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* The attestation report size is the maximum of the attestation report size of APM and CC.
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*
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* hSubDevice: [IN]
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* Subdevice handle for the GPU queried
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* nonce: [IN]
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* spdm supports 32 bytes on nonce
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* attestationReport: [OUT]
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* Attestation report of the GPU queried
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* attestationReportSize: [OUT]
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* Actual size of the report
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* isCecAttestationReportPresent : [OUT]
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* Indicates if the next 2 feilds are valid
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* cecAttestationReport: [OUT]
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* Cec attestation report for the gpu queried
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* cecAttestationReportSize: [OUT]
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* Actual size of the cec attestation report
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT (0xcb33010a) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xA" */
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#define NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE 0x2000
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#define NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE 0x1000
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#define NV_CONF_COMPUTE_NONCE_SIZE 0x20
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#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID (0xAU)
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS {
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NvHandle hSubDevice;
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NvU8 nonce[NV_CONF_COMPUTE_NONCE_SIZE];
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NvU8 attestationReport[NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE];
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NvU32 attestationReportSize;
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NvBool isCecAttestationReportPresent;
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NvU8 cecAttestationReport[NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE];
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NvU32 cecAttestationReportSize;
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} NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS;
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS
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* This control call returns the max number of Conf Compute capable channels SEC2 and CE support.
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*
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* hSubDevice: [IN]
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* subdevice handle for the GPU queried
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* maxSec2Channels: [OUT]
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* Max number of conf compute capable channels SEC2 supports
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* maxCeChannels: [OUT]
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* Max number of channels CE supports with encrypt/decrypt
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS (0xcb33010b) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xB" */
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xBU)
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS {
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NvHandle hSubDevice;
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NvU32 maxSec2Channels;
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NvU32 maxCeChannels;
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} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS;
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/*
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* NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE
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* This control call returns if key rotation is enabled.
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*
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* hSubDevice: [IN]
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* subdevice handle for the GPU queried
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* keyRotationState: [OUT]
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* NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_* value
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*
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* Possible return values:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_OBJECT_NOT_FOUND
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*/
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE (0xcb33010c) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xC" */
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED 0 // key rotation is disabled
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED 1 // key rotation enabled for kernel keys
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED 2 // key rotation enabled for user keys
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED 3 // key rotation enabled for both keys
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#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID (0xCU)
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typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS {
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NvHandle hSubDevice;
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NvU32 keyRotationState;
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} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS;
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/* _ctrlcb33_h_ */
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