mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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464 lines
15 KiB
C++
464 lines
15 KiB
C++
/*
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* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/******************************* List **************************************\
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* *
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* Module: dp_linkconfig.h *
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* Link Configuration object implementation *
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* *
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\***************************************************************************/
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#ifndef INCLUDED_DP_LINKCONFIG_H
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#define INCLUDED_DP_LINKCONFIG_H
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#include "dp_auxdefs.h"
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#include "dp_internal.h"
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#include "dp_watermark.h"
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#include "ctrl/ctrl0073/ctrl0073specific.h" // NV0073_CTRL_HDCP_VPRIME_SIZE
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#include "displayport.h"
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namespace DisplayPort
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{
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typedef NvU64 LinkRate;
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class LinkRates : virtual public Object
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{
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public:
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// Store link rate in multipler of 270MBPS to save space
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NvU8 element[NV_DPCD_SUPPORTED_LINK_RATES__SIZE];
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NvU8 entries;
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LinkRates()
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{
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entries = 0;
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for (int i = 0; i < NV_DPCD_SUPPORTED_LINK_RATES__SIZE; i++)
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{
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element[i] = 0;
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}
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}
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void clear()
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{
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entries = 0;
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for (int i = 0; i < NV_DPCD_SUPPORTED_LINK_RATES__SIZE; i++)
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{
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element[i] = 0;
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}
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}
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bool import(NvU8 linkBw)
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{
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if (entries < NV_DPCD_SUPPORTED_LINK_RATES__SIZE)
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{
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element[entries] = linkBw;
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entries++;
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return true;
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}
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else
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return false;
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}
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NvU8 getNumLinkRates()
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{
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return entries;
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}
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LinkRate getLowerRate(LinkRate rate)
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{
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int i;
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NvU8 linkBw = (NvU8)(rate / DP_LINK_BW_FREQ_MULTI_MBPS);
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if ((entries == 0) || (linkBw <= element[0]))
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return 0;
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for (i = entries - 1; i > 0; i--)
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{
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if (linkBw > element[i])
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break;
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}
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rate = (LinkRate)element[i] * DP_LINK_BW_FREQ_MULTI_MBPS;
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return rate;
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}
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LinkRate getMaxRate()
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{
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LinkRate rate = 0;
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if ((entries > 0) &&
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(entries <= NV_DPCD_SUPPORTED_LINK_RATES__SIZE))
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{
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rate = (LinkRate)element[entries - 1] * DP_LINK_BW_FREQ_MULTI_MBPS;
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}
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return rate;
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}
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};
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class LinkPolicy : virtual public Object
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{
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bool bNoFallback; // No fallback when LT fails
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LinkRates linkRates;
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public:
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LinkPolicy() : bNoFallback(false)
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{
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}
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bool skipFallback()
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{
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return bNoFallback;
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}
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void setSkipFallBack(bool bSkipFallback)
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{
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bNoFallback = bSkipFallback;
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}
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LinkRates *getLinkRates()
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{
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return &linkRates;
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}
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};
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enum
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{
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totalTimeslots = 64,
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totalUsableTimeslots = totalTimeslots - 1
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};
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// in MBps
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enum
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{
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RBR = 162000000,
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EDP_2_16GHZ = 216000000,
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EDP_2_43GHZ = 243000000,
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HBR = 270000000,
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EDP_3_24GHZ = 324000000,
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EDP_4_32GHZ = 432000000,
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HBR2 = 540000000,
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EDP_6_75GHZ = 675000000,
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HBR3 = 810000000
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};
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struct HDCPState
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{
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bool HDCP_State_Encryption;
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bool HDCP_State_1X_Capable;
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bool HDCP_State_22_Capable;
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bool HDCP_State_Authenticated;
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bool HDCP_State_Repeater_Capable;
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};
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struct HDCPValidateData
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{
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};
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typedef enum
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{
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DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE,
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DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST,
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DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST,
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}DP_SINGLE_HEAD_MULTI_STREAM_MODE;
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#define HEAD_INVALID_STREAMS 0
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#define HEAD_DEFAULT_STREAMS 1
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typedef enum
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{
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DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY = 0,
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DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_SECONDARY = 1,
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DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_MAX = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_SECONDARY,
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} DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID;
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#define DP_INVALID_SOR_INDEX 0xFFFFFFFF
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#define DSC_DEPTH_FACTOR 16
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class LinkConfiguration : virtual public Object
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{
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public:
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LinkPolicy policy;
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unsigned lanes;
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LinkRate peakRatePossible;
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LinkRate peakRate;
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LinkRate minRate;
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bool enhancedFraming;
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bool multistream;
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bool disablePostLTRequest;
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bool bEnableFEC;
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bool bDisableLTTPR;
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//
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// The counter to record how many times link training happens.
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// Client can reset the counter by calling setLTCounter(0)
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//
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unsigned linkTrainCounter;
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LinkConfiguration() :
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lanes(0), peakRatePossible(0), peakRate(0), minRate(0),
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enhancedFraming(false), multistream(false), disablePostLTRequest(false),
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bEnableFEC(false), bDisableLTTPR(false), linkTrainCounter(0) {};
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LinkConfiguration(LinkPolicy * p, unsigned lanes, LinkRate peakRate,
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bool enhancedFraming, bool MST, bool disablePostLTRequest = false,
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bool bEnableFEC = false, bool bDisableLTTPR = false) :
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lanes(lanes), peakRatePossible(peakRate), peakRate(peakRate),
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enhancedFraming(enhancedFraming), multistream(MST),
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disablePostLTRequest(disablePostLTRequest),
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bEnableFEC(bEnableFEC), bDisableLTTPR(bDisableLTTPR),
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linkTrainCounter(0)
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{
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// downrate for spread and FEC
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minRate = linkOverhead(peakRate);
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if (p)
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{
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policy = *p;
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}
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}
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void setLTCounter(unsigned counter)
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{
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linkTrainCounter = counter;
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}
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unsigned getLTCounter()
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{
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return linkTrainCounter;
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}
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NvU64 linkOverhead(NvU64 rate)
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{
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if(bEnableFEC)
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{
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// if FEC is enabled, we have to account for 3% overhead
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// for FEC+downspread according to DP 1.4 spec
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return rate - 3 * rate/ 100;
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}
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else
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{
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// if FEC is not enabled, link overhead comprises only of
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// 0.05% downspread.
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return rate - 5 * rate/ 1000;
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}
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}
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void enableFEC(bool setFEC)
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{
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bEnableFEC = setFEC;
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// If FEC is enabled, update minRate with FEC+downspread overhead.
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minRate = linkOverhead(peakRate);
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}
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LinkConfiguration(unsigned long TotalLinkPBN)
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: enhancedFraming(true),
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multistream(true),
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disablePostLTRequest(false),
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bEnableFEC(false),
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bDisableLTTPR(false),
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linkTrainCounter(0)
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{
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// Reverse engineer a link configuration from Total TotalLinkPBN
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// Note that HBR2 twice HBR. The table below treats HBR2x1 and HBRx2, etc.
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//
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// BW Effective Lanes Total TotalLinkPBN
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// 165 1 195.5555556
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// 165 2 391.1111111
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// 165 4 782.2222222
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// 270 1 320
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// 270 2 640
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// 270 4 1280
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// 270 8 2560
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//
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if (TotalLinkPBN <= 90)
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peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes=0; // FAIL
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if (TotalLinkPBN <= 195)
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peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes=1;
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else if (TotalLinkPBN <= 320)
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peakRatePossible = peakRate = HBR, minRate=linkOverhead(HBR), lanes = 1;
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else if (TotalLinkPBN <= 391)
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peakRatePossible = peakRate = RBR, minRate=linkOverhead(RBR), lanes = 2;
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else if (TotalLinkPBN <= 640)
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peakRatePossible = peakRate = HBR, minRate=linkOverhead(HBR), lanes = 2; // could be HBR2x1, but TotalLinkPBN works out same
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else if (TotalLinkPBN <= 782)
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peakRatePossible = peakRate = RBR, minRate=linkOverhead(RBR), lanes = 4;
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else if (TotalLinkPBN <= 960)
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peakRatePossible = peakRate = HBR3, minRate=linkOverhead(HBR3), lanes = 1;
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else if (TotalLinkPBN <= 1280)
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peakRatePossible = peakRate = HBR, minRate=linkOverhead(HBR), lanes = 4; // could be HBR2x2
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else if (TotalLinkPBN <= 1920)
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peakRatePossible = peakRate = HBR3, minRate=linkOverhead(HBR3), lanes = 2; // could be HBR2x
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else if (TotalLinkPBN <= 2560)
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peakRatePossible = peakRate = HBR2, minRate=linkOverhead(HBR2), lanes = 4;
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else if (TotalLinkPBN <= 3840)
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peakRatePossible = peakRate = HBR3, minRate=linkOverhead(HBR3), lanes = 4;
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else {
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peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes = 0; // FAIL
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DP_ASSERT(0 && "Unknown configuration");
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}
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}
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void setEnhancedFraming(bool newEnhancedFraming)
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{
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enhancedFraming = newEnhancedFraming;
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}
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bool isValid()
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{
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return lanes != laneCount_0;
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}
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bool lowerConfig(bool bReduceLaneCnt = false)
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{
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//
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// TODO: bReduceLaneCnt is set to fallback to 4 lanes with lower
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// valid link rate. But we should reset to max lane count
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// sink supports instead.
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//
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LinkRate lowerRate = policy.getLinkRates()->getLowerRate(peakRate);
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if(bReduceLaneCnt)
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{
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// Reduce laneCount before reducing linkRate
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if(lanes == laneCount_1)
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{
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if (lowerRate)
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{
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lanes = laneCount_4;
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peakRate = lowerRate;
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}
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else
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{
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lanes = laneCount_0;
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}
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}
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else
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{
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lanes /= 2;
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}
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}
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else
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{
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// Reduce the link rate instead of lane count
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if (lowerRate)
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{
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peakRate = lowerRate;
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}
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else
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{
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lanes /= 2;
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}
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}
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minRate = linkOverhead(peakRate);
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return lanes != laneCount_0;
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}
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void setLaneRate(LinkRate newRate, unsigned newLanes)
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{
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peakRate = newRate;
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lanes = newLanes;
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minRate = linkOverhead(peakRate);
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}
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unsigned pbnTotal()
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{
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return PBNForSlots(totalUsableTimeslots);
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}
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void pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn)
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{
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base_pbn = pbnForMode(modesetInfo);
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if (bEnableFEC)
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{
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// IF FEC is enabled, we need to consider 3% overhead as per DP1.4 spec.
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base_pbn = (NvU32)(divide_ceil(base_pbn * 100, 97));
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}
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slots = slotsForPBN(base_pbn);
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slots_pbn = PBNForSlots(slots);
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}
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NvU32 slotsForPBN(NvU32 allocatedPBN, bool usable = false)
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{
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NvU64 bytes_per_pbn = 54 * 1000000 / 64; // this comes out exact
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NvU64 bytes_per_timeslot = peakRate * lanes / 64;
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if (bytes_per_timeslot == 0)
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return (NvU32)-1;
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if (usable)
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{
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// round down to find the usable integral slots for a given value of PBN.
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NvU32 slots = (NvU32)divide_floor(allocatedPBN * bytes_per_pbn, bytes_per_timeslot);
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DP_ASSERT(slots <= 64);
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return slots;
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}
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else
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return (NvU32)divide_ceil(allocatedPBN * bytes_per_pbn, bytes_per_timeslot);
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}
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NvU32 PBNForSlots(NvU32 slots) // Rounded down
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{
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NvU64 bytes_per_pbn = 54 * 1000000 / 64; // this comes out exact
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NvU64 bytes_per_timeslot = peakRate * lanes / 64;
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return (NvU32)(bytes_per_timeslot * slots/ bytes_per_pbn);
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}
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bool operator!= (const LinkConfiguration & right) const
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{
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return !(*this == right);
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}
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bool operator== (const LinkConfiguration & right) const
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{
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return (this->lanes == right.lanes &&
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this->peakRate == right.peakRate &&
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this->enhancedFraming == right.enhancedFraming &&
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this->multistream == right.multistream &&
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this->bEnableFEC == right.bEnableFEC);
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}
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bool operator< (const LinkConfiguration & right) const
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{
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NvU64 leftMKBps = peakRate * lanes;
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NvU64 rightMKBps = right.peakRate * right.lanes;
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if (leftMKBps == rightMKBps)
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{
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return (lanes < right.lanes);
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}
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else
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{
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return (leftMKBps < rightMKBps);
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}
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}
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};
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}
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#endif //INCLUDED_DP_LINKCONFIG_H
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