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560 lines
18 KiB
C
560 lines
18 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn
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//
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#include "ctrl/ctrlb0cc/ctrlb0ccbase.h"
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/*!
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* NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY
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*
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* Reserves the HWPM legacy PM system for use by the calling client.
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* This PM system will only be accessible if this reservation is
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* taken.
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*
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* If a device level reservation is held by another client, then this command
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* will fail regardless of reservation scope.
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*
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* This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY.
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*
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*/
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#define NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY (0xb0cc0101) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0x1U)
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typedef struct NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS {
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/*!
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* [in] Enable ctxsw for HWPM.
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*/
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NvBool ctxsw;
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} NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY
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*
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* Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
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*
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* This command does not take any parameters.
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*
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*/
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#define NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY (0xb0cc0102) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x2" */
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/*!
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* NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC
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*
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* Reserves the SMPC PM system for use by the calling client.
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* This PM system will only be accessible if this reservation is
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* taken.
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*
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* Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
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*
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* This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC.
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*
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*/
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#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC (0xb0cc0103) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID (0x3U)
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typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS {
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/*!
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* [in] Enable ctxsw for SMPC.
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*/
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NvBool ctxsw;
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} NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC
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*
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* Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC.
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*
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* This command does not take any parameters.
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*
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*/
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#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC (0xb0cc0104) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x4" */
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/*!
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* NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM
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*
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* Allocates PMA VA and map it to the buffers for streaming records and for
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* for streaming the updated bytes available in the buffer.
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*
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*/
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#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */
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/*!
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* Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page
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* reserved for streaming mem_bytes (see @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE).
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*/
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#define NVB0CC_PMA_BUFFER_SIZE_MAX (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */
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#define NVB0CC_PMA_BYTES_AVAILABLE_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */
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#define NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x5U)
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typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS {
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/*!
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* [in] Memory handle (RW memory) for streaming records.
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* Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize.
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*/
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NvHandle hMemPmaBuffer;
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/*!
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* [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer).
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*/
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NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8);
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/*!
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* [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX.
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*/
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NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8);
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/*!
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* [in] Memory handle (RO memory) for streaming number of bytes available.
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* Size of this must be of at least @ref pmaBytesAvailableOffset +
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* @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE.
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*/
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NvHandle hMemPmaBytesAvailable;
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/*!
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* [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable).
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*/
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NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8);
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/*!
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* [in] Enable ctxsw for PMA stream.
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*/
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NvBool ctxsw;
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/*!
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* [out] The PMA Channel Index associated with a given PMA stream.
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*/
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NvU32 pmaChannelIdx;
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/*!
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* [out] PMA buffer VA. Note that this is a HWPM Virtual address.
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*/
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NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8);
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} NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_FREE_PMA_STREAM
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*
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* Releases (unmap and free) PMA stream allocated through
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* @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM.
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*
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*/
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#define NVB0CC_CTRL_CMD_FREE_PMA_STREAM (0xb0cc0106) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U)
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typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS {
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/*!
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* [in] The PMA channel index associated with a given PMA stream.
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*/
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NvU32 pmaChannelIdx;
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} NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_BIND_PM_RESOURCES
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*
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* Binds all PM resources reserved through @ref NVB0CC_CTRL_CMD_RESERVE_*
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* and with @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM with PMA engine.
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* After this call, interface is ready for programming a collection
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* of counters.
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* @Note: Any new PM resource reservation via NVB0CC_CTRL_CMD_RESERVE_* or
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* @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM request after this call will fail,
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* clients need to unbind (see @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES) to
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* reserve more resources.
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*
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* This can be unbound with @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES.
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*
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*/
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#define NVB0CC_CTRL_CMD_BIND_PM_RESOURCES (0xb0cc0107) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x7" */
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/*!
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* NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES
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*
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* Unbinds PM resources that were bound with @ref NVB0CC_CTRL_CMD_BIND_PM_RESOURCES
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*
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*/
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#define NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES (0xb0cc0108) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x8" */
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/*!
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* NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT
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*
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* This command updates bytes consumed by the SW and optionally gets the
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* current available bytes in the buffer.
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*
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*/
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#define NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT (0xb0cc0109) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID" */
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#define NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE 0xFFFFFFFF
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#define NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID (0x9U)
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typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS {
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/*!
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* [in] Total bytes consumed by SW since last update.
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*/
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NV_DECLARE_ALIGNED(NvU64 bytesConsumed, 8);
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/*!
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* [in] Initiate streaming of the bytes available (see @ref hMemPmaBytesAvailable).
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* RM will set the memory for streaming (see @ref hMemPmaBytesAvailable) to NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE and
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* client can optionally wait (see @ref bWait) for it to change from this value.
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*/
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NvBool bUpdateAvailableBytes;
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/*!
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* [in] Waits for available bytes to get updated
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*/
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NvBool bWait;
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/*!
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* [out] Bytes available in the PMA buffer (see @ref hMemPmaBuffer) for SW to consume.
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* This will only be populated if both bUpdateAvailableBytes and bWait are set
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* to TRUE.
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*/
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NV_DECLARE_ALIGNED(NvU64 bytesAvailable, 8);
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/*!
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* [in] If set to TRUE, current put pointer will be returned in @ref putPtr.
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*/
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NvBool bReturnPut;
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/*!
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* [out] Current PUT pointer (MEM_HEAD).
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* This will only be populated if bReturnPut is set to TRUE.
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*/
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NV_DECLARE_ALIGNED(NvU64 putPtr, 8);
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/*!
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* [in] The PMA Channel Index associated with a given PMA stream.
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*/
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NvU32 pmaChannelIdx;
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/*!
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* [out] Set to TRUE if PMA buffer has overflowed.
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*/
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NvBool bOverflowStatus;
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} NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS;
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/*!
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* Maximum number of register operations allowed in a single request.
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* @NOTE: @ref NVB0CC_REGOPS_MAX_COUNT is chosen to keep struct size
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* of @ref NVB0CC_CTRL_EXEC_REG_OPS_PARAMS under 4KB.
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*/
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#define NVB0CC_REGOPS_MAX_COUNT (124)
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/*!
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* NVB0CC_CTRL_CMD_EXEC_REG_OPS
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*
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* This command is used to submit an array containing one or more
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* register operations for processing. Each entry in the
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* array specifies a single read or write operation. Each entry is
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* checked for validity in the initial pass: Only registers from PM area
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* are allowed using this interface and only register from PM systems for
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* which user has a valid reservation are allowed (see @ref NVB0CC_CTRL_CMD_RESERVE_*).
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* Operation type (@ref NV2080_CTRL_GPU_REG_OP_TYPE_*) is not required to be passed in.
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*/
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#define NVB0CC_CTRL_CMD_EXEC_REG_OPS (0xb0cc010a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */
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/*!
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* Structure definition for register operation. See @ref NV2080_CTRL_GPU_REG_OP.
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*/
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typedef NV2080_CTRL_GPU_REG_OP NVB0CC_GPU_REG_OP;
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/*!
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* Enumeration of different REG_OPS modes. This mode determines how a failure
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* of a regop is handled in a batch of regops.
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*/
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typedef enum NVB0CC_REGOPS_MODE {
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/*!
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* Either all regops will be executed or none of them will be executed.
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* Failing regop will have the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus).
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*/
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NVB0CC_REGOPS_MODE_ALL_OR_NONE = 0,
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/*!
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* All regops will be attempted and the ones that failed will have the
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* the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus).
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*/
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NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR = 1,
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} NVB0CC_REGOPS_MODE;
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#define NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0xAU)
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typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS {
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/*!
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* [in] Number of valid entries in the regOps array. This value cannot
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* exceed NVB0CC_REGOPS_MAX_COUNT.
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*/
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NvU32 regOpCount;
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/*!
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* [in] Specifies the mode for the entire operation see @ref NVB0CC_REGOPS_MODE.
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*/
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NVB0CC_REGOPS_MODE mode;
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/*!
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* [out] Provides status for the entire operation. This is only valid for
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* mode @ref NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR.
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*/
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NvBool bPassed;
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/*!
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* [out] This is currently not populated.
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*/
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NvBool bDirect;
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/*!
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* [in/out] An array (of fixed size NVB0CC_REGOPS_MAX_COUNT) of register read or write
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* operations (see @ref NVB0CC_GPU_REG_OP)
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*
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*/
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NVB0CC_GPU_REG_OP regOps[NVB0CC_REGOPS_MAX_COUNT];
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} NVB0CC_CTRL_EXEC_REG_OPS_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER
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*
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* Reserves the PC sampler system for use by the calling client.
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*
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* This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER.
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*
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* This command does not take any parameters.
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*
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* PC sampler is always context switched with a GR context, so reservation scope is
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* always context. This requires that profiler object is instantiated with a valid GR
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* context. See @ref NVB2CC_ALLOC_PARAMETERS.
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*/
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#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER (0xb0cc010b) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xB" */
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/*!
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* NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER
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*
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* Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER.
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*
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* This command does not take any parameters.
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*
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*/
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#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER (0xb0cc010c) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xC" */
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/*!
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* NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS
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*
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* Gets the total high speed streaming credits available for the client.
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*
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* This command can only be performed after a bind using NVB0CC_CTRL_CMD_BIND_PM_RESOURCES.
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*
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*/
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#define NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS (0xb0cc010d) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID (0xDU)
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typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS {
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NvU32 numCredits;
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} NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_SET_HS_CREDITS_CHIPLET
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*
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* Sets per chiplet (pmm router) credits for high speed streaming for a pma channel.
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*
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* @note: This command resets the current credits to 0 before setting the new values also
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* if programming fails, it will reset credits to 0 for all the chiplets.
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*
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*/
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#define NVB0CC_CTRL_CMD_SET_HS_CREDITS (0xb0cc010e) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID" */
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typedef enum NVB0CC_CHIPLET_TYPE {
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NVB0CC_CHIPLET_TYPE_INVALID = 0,
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NVB0CC_CHIPLET_TYPE_FBP = 1,
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NVB0CC_CHIPLET_TYPE_GPC = 2,
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NVB0CC_CHIPLET_TYPE_SYS = 3,
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} NVB0CC_CHIPLET_TYPE;
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typedef enum NVB0CC_HS_CREDITS_CMD_STATUS {
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NVB0CC_HS_CREDITS_CMD_STATUS_OK = 0,
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/*!
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* More credits are requested than the total credits. Total credits can be queried using @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS
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*/
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NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS = 1,
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/*!
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* Chiplet index is invalid.
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*/
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NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET = 2,
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} NVB0CC_HS_CREDITS_CMD_STATUS;
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typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO {
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/*!
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* Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE.
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*/
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NvU8 chipletType;
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/*!
|
|
* Specifies the logical index of the chiplet.
|
|
*/
|
|
NvU8 chipletIndex;
|
|
|
|
/*!
|
|
* Specifies the number of credits for the chiplet.
|
|
*/
|
|
NvU16 numCredits;
|
|
} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO;
|
|
|
|
typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS {
|
|
/*!
|
|
* Status for the command @ref NVB0CC_HS_CREDITS_CMD_STATUS.
|
|
*/
|
|
NvU8 status;
|
|
|
|
/*!
|
|
* Index of the failing @ref NVB0CC_CTRL_SET_HS_CREDITS_PARAMS::creditInfo entry. This
|
|
* is only relevant if status is NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET.
|
|
*/
|
|
NvU8 entryIndex;
|
|
} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS;
|
|
|
|
#define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63)
|
|
|
|
typedef struct NVB0CC_CTRL_HS_CREDITS_PARAMS {
|
|
/*!
|
|
* [in] The PMA Channel Index associated with a given PMA stream.
|
|
*/
|
|
NvU8 pmaChannelIdx;
|
|
|
|
/*!
|
|
* [in] Number of valid entries in creditInfo.
|
|
*/
|
|
NvU8 numEntries;
|
|
|
|
/*!
|
|
* [out] Provides status for the entire operation.
|
|
*/
|
|
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS statusInfo;
|
|
|
|
/*!
|
|
* [in] Credit programming per chiplet
|
|
*/
|
|
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES];
|
|
} NVB0CC_CTRL_HS_CREDITS_PARAMS;
|
|
|
|
#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU)
|
|
|
|
typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_SET_HS_CREDITS_PARAMS;
|
|
|
|
/*!
|
|
* NVB0CC_CTRL_CMD_GET_HS_CREDITS
|
|
*
|
|
* Gets per chiplet (pmm router) high speed streaming credits for a pma channel.
|
|
*
|
|
*/
|
|
#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID" */
|
|
|
|
#define NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID (0xFU)
|
|
|
|
typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS;
|
|
|
|
|
|
|
|
typedef enum NVB0CC_CTRL_HES_TYPE {
|
|
NVB0CC_CTRL_HES_INVALID = 0,
|
|
NVB0CC_CTRL_HES_CWD = 1,
|
|
} NVB0CC_CTRL_HES_TYPE;
|
|
|
|
typedef struct NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS {
|
|
/*!
|
|
* [in] Enable ctxsw for HES_CWD.
|
|
*/
|
|
NvBool ctxsw;
|
|
} NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS;
|
|
|
|
/*
|
|
* NVB0CC_CTRL_HES_RESERVATION_UNION
|
|
*
|
|
* Union of all HES reservation params
|
|
*
|
|
*/
|
|
typedef union NVB0CC_CTRL_HES_RESERVATION_UNION {
|
|
NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS cwd;
|
|
} NVB0CC_CTRL_HES_RESERVATION_UNION;
|
|
|
|
/*!
|
|
* NVB0CC_CTRL_CMD_RESERVE_HES
|
|
*
|
|
* Reserves HES for use by the calling client.
|
|
* This PM system will only be accessible if this reservation is
|
|
* taken.
|
|
*
|
|
* This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HES.
|
|
*
|
|
* Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
|
|
*
|
|
*/
|
|
#define NVB0CC_CTRL_CMD_RESERVE_HES (0xb0cc0113) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID" */
|
|
|
|
#define NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID (0x13U)
|
|
|
|
typedef struct NVB0CC_CTRL_RESERVE_HES_PARAMS {
|
|
/*!
|
|
* [in] Denotes the HES reservation type. Choose from @NVB0CC_CTRL_HES_TYPE.
|
|
*/
|
|
NvU32 type;
|
|
|
|
/*!
|
|
* [in] Union of all possible reserve param structs. Initialize the reserveParams corresponding to the chosen type.
|
|
*/
|
|
NVB0CC_CTRL_HES_RESERVATION_UNION reserveParams;
|
|
} NVB0CC_CTRL_RESERVE_HES_PARAMS;
|
|
|
|
/*!
|
|
* NVB0CC_CTRL_CMD_RELEASE_HES
|
|
*
|
|
* Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HES.
|
|
*
|
|
*/
|
|
#define NVB0CC_CTRL_CMD_RELEASE_HES (0xb0cc0114) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID" */
|
|
|
|
#define NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID (0x14U)
|
|
|
|
typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS {
|
|
/*!
|
|
* [in] type of @NVB0CC_CTRL_HES_TYPE needs to be released.
|
|
*/
|
|
NVB0CC_CTRL_HES_TYPE type;
|
|
} NVB0CC_CTRL_RELEASE_HES_PARAMS;
|
|
|
|
/* _ctrlb0ccprofiler_h_ */
|