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91 lines
3.1 KiB
C
91 lines
3.1 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2000-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef HWBC_H
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#define HWBC_H
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#include "gpu/gpu.h" // NBADDR, OBJGPU
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/**************** Resource Manager Defines and Structures ******************\
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* *
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* Module: HWBC.H *
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* Hardware Broadcast related defines and structures. *
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* *
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\***************************************************************************/
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struct OBJCL;
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typedef struct OBJHWBC OBJHWBC;
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#define BR03_GPU_REGISTER_ALIAS_OFFSET 0x4FC000
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NvBool objClSetPcieHWBC(OBJGPU *, OBJCL*); // Find all Broadcast resource in the higher hierarchy of the GPU
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//
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// Bridge resource type
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//
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typedef
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enum {
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HWBC_UNKNOWN = 0
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, HWBC_NVIDIA_BR03
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, HWBC_NVIDIA_BR04
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, HWBC_PLX_PEX8747
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} HWBC_RES_TYPE;
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struct OBJHWBC
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{
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// what kind of BC resource
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HWBC_RES_TYPE bcRes;
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NvU32 hwbcId;
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// the control device
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// this would be the upstream port for BR03 or the host bridge for C19/CK804
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NBADDR ctrlDev;
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// any device has bus number between the minBus and maxBus(inclusive) is connected to this device
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// this equals to the secondary bus number and subordinate bus number for a bridge (BR03)
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NvU32 domain;
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NvU8 minBus, maxBus;
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OBJHWBC *pSibling, *pFirstChild, *pParent; // link to siblings, the first child and parent
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NvU32 gpuMask;
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RmPhysAddr gpuPhysAddr;
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// Private data
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NvBool hasPlxFirmwareInfo;
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NvU32 fwVersion;
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NvU8 fwOemVersion;
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NvU8 plxRevision;
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NvBool bNotInBoard;
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};
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void plxPex8747GetFirmwareInfo(OBJCL *pCl, OBJGPU *pGpu, OBJHWBC *pHWBC);
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//
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// Hardware Broadcast error conditions
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#define HWBC_ERROR_BR03_INVALID_BAR0 0
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#endif // HWBC_H
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