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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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184 lines
7.3 KiB
C
184 lines
7.3 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrlb069.finn
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//
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#include "ctrl/ctrlxxxx.h"
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/* MAXWELL_FAULT_BUFFER_A control commands and parameters */
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#define NVB069_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xB069, NVB069_CTRL_##cat, idx)
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/* MAXWELL_FAULT_BUFFER_A command categories (6bits) */
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#define NVB069_CTRL_RESERVED (0x00)
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#define NVB069_CTRL_FAULTBUFFER (0x01)
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/*
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* NVB069_CTRL_CMD_NULL
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*
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* This command does nothing.
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* This command does not take any parameters.
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NVB069_CTRL_CMD_NULL (0xb0690000) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
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/*
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* NVB069_CTRL_CMD_FAULTBUFFER_READ_GET
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*
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* This command returns the current HW GET pointer for the requested type fault buffer
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*
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* faultBufferGetOffset
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* Value of current HW GET pointer
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* faultBufferType
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* Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE
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*/
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#define NVB069_CTRL_CMD_FAULTBUFFER_READ_GET (0xb0690101) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID" */
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#define NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U)
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typedef struct NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS {
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NvU32 faultBufferGetOffset;
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NvU32 faultBufferType;
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} NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS;
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//
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// Valid Fault buffer Types
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// NON_REPLAYABLE is only supported in Volta+ GPUs.
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//
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#define NVB069_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000)
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#define NVB069_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001)
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/*
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* NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET
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*
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* This command writes the HW GET pointer for the requested type of fault buffer
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*
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* NOTE: The caller must issue a write barrier before this function to
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* ensure modifications to the current buffer entry are committed before
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* the GET pointer is updated.
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*
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* faultBufferGetOffset
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* Value to be written to HW GET pointer
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* faultBufferType
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* Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE
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*/
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#define NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET (0xb0690102) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */
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#define NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U)
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typedef struct NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS {
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NvU32 faultBufferGetOffset;
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NvU32 faultBufferType;
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} NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS;
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/*
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* NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT
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*
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* This command returns the current HW PUT pointer for the requested type fault buffer
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*
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* faultBufferGetOffset
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* Value of current HW PUT pointer
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* faultBufferType
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* Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE
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*/
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#define NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT (0xb0690103) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID" */
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#define NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U)
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typedef struct NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS {
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NvU32 faultBufferPutOffset;
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NvU32 faultBufferType;
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} NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS;
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#define NVB069_CTRL_CMD_FAULTBUFFER_ENABLE_NOTIFICATION (0xb0690104) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS_MESSAGE_ID" */
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#define NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS_MESSAGE_ID (0x4U)
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typedef struct NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS {
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NvBool Enable;
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} NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS;
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#define NVB069_CTRL_CMD_FAULTBUFFER_GET_SIZE (0xb0690105) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */
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#define NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U)
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typedef struct NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS {
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NvU32 faultBufferSize;
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} NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS;
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/*
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* NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS
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*
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* This command provides kernel mapping to a few registers.
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* These mappings are needed by UVM driver to handle non fatal gpu faults
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*
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* pFaultBufferGet
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* Mapping for fault buffer's get pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_GET)
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* pFaultBufferPut
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* Mapping for fault buffer's put pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_PUT)
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* pFaultBufferInfo
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* Mapping for fault buffer's Info pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_INFO)
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* Note: this variable is deprecated since buffer overflow is not a seperate register from Volta
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* pPmcIntr
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* Mapping for PMC intr register (NV_PMC_INTR(0))
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* pPmcIntrEnSet
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* Mapping for PMC intr set register - used to enable an intr (NV_PMC_INTR_EN_SET(0))
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* pPmcIntrEnClear
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* Mapping for PMC intr clear register - used to disable an intr (NV_PMC_INTR_EN_CLEAR(0))
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* replayableFaultMask
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* Mask for the replayable fault bit(NV_PMC_INTR_REPLAYABLE_FAULT)
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* faultBufferType
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* This is an input param denoting replayable/non-replayable fault buffer
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*/
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#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS (0xb0690106) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */
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#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U)
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typedef struct NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS {
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NV_DECLARE_ALIGNED(NvP64 pFaultBufferGet, 8);
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NV_DECLARE_ALIGNED(NvP64 pFaultBufferPut, 8);
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NV_DECLARE_ALIGNED(NvP64 pFaultBufferInfo, 8);
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NV_DECLARE_ALIGNED(NvP64 pPmcIntr, 8);
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NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnSet, 8);
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NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnClear, 8);
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NvU32 replayableFaultMask;
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NV_DECLARE_ALIGNED(NvP64 pPrefetchCtrl, 8);
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NvU32 faultBufferType;
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} NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS;
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/* _ctrlb069_h_ */
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