mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-03 06:57:27 +00:00
535 lines
23 KiB
C
535 lines
23 KiB
C
#define NVOC_KERNEL_CE_H_PRIVATE_ACCESS_ALLOWED
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#include "nvoc/runtime.h"
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#include "nvoc/rtti.h"
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#include "nvtypes.h"
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#include "nvport/nvport.h"
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#include "nvport/inline/util_valist.h"
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#include "utils/nvassert.h"
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#include "g_kernel_ce_nvoc.h"
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#ifdef DEBUG
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char __nvoc_class_id_uniqueness_check_0x242aca = 1;
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#endif
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCE;
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object;
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE;
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService;
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void __nvoc_init_KernelCE(KernelCE*, RmHalspecOwner* );
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void __nvoc_init_funcTable_KernelCE(KernelCE*, RmHalspecOwner* );
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NV_STATUS __nvoc_ctor_KernelCE(KernelCE*, RmHalspecOwner* );
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void __nvoc_init_dataField_KernelCE(KernelCE*, RmHalspecOwner* );
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void __nvoc_dtor_KernelCE(KernelCE*);
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extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCE;
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static const struct NVOC_RTTI __nvoc_rtti_KernelCE_KernelCE = {
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/*pClassDef=*/ &__nvoc_class_def_KernelCE,
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/*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelCE,
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/*offset=*/ 0,
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};
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static const struct NVOC_RTTI __nvoc_rtti_KernelCE_Object = {
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/*pClassDef=*/ &__nvoc_class_def_Object,
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/*dtor=*/ &__nvoc_destructFromBase,
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/*offset=*/ NV_OFFSETOF(KernelCE, __nvoc_base_OBJENGSTATE.__nvoc_base_Object),
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};
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static const struct NVOC_RTTI __nvoc_rtti_KernelCE_OBJENGSTATE = {
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/*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE,
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/*dtor=*/ &__nvoc_destructFromBase,
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/*offset=*/ NV_OFFSETOF(KernelCE, __nvoc_base_OBJENGSTATE),
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};
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static const struct NVOC_RTTI __nvoc_rtti_KernelCE_IntrService = {
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/*pClassDef=*/ &__nvoc_class_def_IntrService,
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/*dtor=*/ &__nvoc_destructFromBase,
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/*offset=*/ NV_OFFSETOF(KernelCE, __nvoc_base_IntrService),
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};
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static const struct NVOC_CASTINFO __nvoc_castinfo_KernelCE = {
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/*numRelatives=*/ 4,
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/*relatives=*/ {
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&__nvoc_rtti_KernelCE_KernelCE,
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&__nvoc_rtti_KernelCE_IntrService,
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&__nvoc_rtti_KernelCE_OBJENGSTATE,
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&__nvoc_rtti_KernelCE_Object,
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},
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};
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const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCE =
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{
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/*classInfo=*/ {
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/*size=*/ sizeof(KernelCE),
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/*classId=*/ classId(KernelCE),
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/*providerId=*/ &__nvoc_rtti_provider,
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#if NV_PRINTF_STRINGS_ALLOWED
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/*name=*/ "KernelCE",
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#endif
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},
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/*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelCE,
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/*pCastInfo=*/ &__nvoc_castinfo_KernelCE,
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/*pExportInfo=*/ &__nvoc_export_info_KernelCE
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};
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static NV_STATUS __nvoc_thunk_KernelCE_engstateConstructEngine(OBJGPU *pGpu, struct OBJENGSTATE *pKCe, ENGDESCRIPTOR arg0) {
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return kceConstructEngine(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0);
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}
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static NvBool __nvoc_thunk_KernelCE_engstateIsPresent(OBJGPU *pGpu, struct OBJENGSTATE *pKCe) {
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return kceIsPresent(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset));
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}
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static NV_STATUS __nvoc_thunk_KernelCE_engstateStateLoad(OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) {
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return kceStateLoad(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg2);
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}
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static NV_STATUS __nvoc_thunk_KernelCE_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKCe, NvU32 flags) {
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return kceStateUnload(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), flags);
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}
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static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[168]) {
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kceRegisterIntrService(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2);
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}
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static NV_STATUS __nvoc_thunk_KernelCE_intrservServiceNotificationInterrupt(OBJGPU *arg0, struct IntrService *arg1, IntrServiceServiceNotificationInterruptArguments *arg2) {
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return kceServiceNotificationInterrupt(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2);
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}
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static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStateInitLocked(POBJGPU pGpu, struct KernelCE *pEngstate) {
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return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset));
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}
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static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePreLoad(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) {
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return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0);
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}
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static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePostUnload(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) {
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return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0);
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}
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static void __nvoc_thunk_OBJENGSTATE_kceStateDestroy(POBJGPU pGpu, struct KernelCE *pEngstate) {
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engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset));
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}
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static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePreUnload(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) {
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return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0);
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}
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static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStateInitUnlocked(POBJGPU pGpu, struct KernelCE *pEngstate) {
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return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset));
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}
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static void __nvoc_thunk_OBJENGSTATE_kceInitMissing(POBJGPU pGpu, struct KernelCE *pEngstate) {
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engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset));
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}
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static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePreInitLocked(POBJGPU pGpu, struct KernelCE *pEngstate) {
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return engstateStatePreInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset));
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}
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static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePreInitUnlocked(POBJGPU pGpu, struct KernelCE *pEngstate) {
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return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset));
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}
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static NvBool __nvoc_thunk_IntrService_kceClearInterrupt(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceClearInterruptArguments *pParams) {
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return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelCE_IntrService.offset), pParams);
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}
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static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePostLoad(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) {
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return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0);
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}
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static NvU32 __nvoc_thunk_IntrService_kceServiceInterrupt(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceServiceInterruptArguments *pParams) {
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return intrservServiceInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelCE_IntrService.offset), pParams);
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}
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const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCE =
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{
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/*numEntries=*/ 0,
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/*pExportEntries=*/ 0
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};
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void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*);
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void __nvoc_dtor_IntrService(IntrService*);
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void __nvoc_dtor_KernelCE(KernelCE *pThis) {
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__nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE);
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__nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService);
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PORT_UNREFERENCED_VARIABLE(pThis);
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}
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void __nvoc_init_dataField_KernelCE(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) {
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ChipHal *chipHal = &pRmhalspecowner->chipHal;
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const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
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RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
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const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
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PORT_UNREFERENCED_VARIABLE(pThis);
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PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
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PORT_UNREFERENCED_VARIABLE(chipHal);
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PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
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PORT_UNREFERENCED_VARIABLE(rmVariantHal);
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PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
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}
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NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* );
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NV_STATUS __nvoc_ctor_IntrService(IntrService* );
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NV_STATUS __nvoc_ctor_KernelCE(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) {
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NV_STATUS status = NV_OK;
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status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE);
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if (status != NV_OK) goto __nvoc_ctor_KernelCE_fail_OBJENGSTATE;
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status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService);
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if (status != NV_OK) goto __nvoc_ctor_KernelCE_fail_IntrService;
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__nvoc_init_dataField_KernelCE(pThis, pRmhalspecowner);
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goto __nvoc_ctor_KernelCE_exit; // Success
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__nvoc_ctor_KernelCE_fail_IntrService:
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__nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE);
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__nvoc_ctor_KernelCE_fail_OBJENGSTATE:
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__nvoc_ctor_KernelCE_exit:
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return status;
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}
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static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) {
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ChipHal *chipHal = &pRmhalspecowner->chipHal;
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const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
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RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
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const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
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PORT_UNREFERENCED_VARIABLE(pThis);
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PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
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PORT_UNREFERENCED_VARIABLE(chipHal);
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PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
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PORT_UNREFERENCED_VARIABLE(rmVariantHal);
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PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
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pThis->__kceConstructEngine__ = &kceConstructEngine_IMPL;
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// Hal function -- kceIsPresent
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pThis->__kceIsPresent__ = &kceIsPresent_IMPL;
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// Hal function -- kceStateLoad
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pThis->__kceStateLoad__ = &kceStateLoad_GP100;
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// Hal function -- kceStateUnload
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// default
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pThis->__kceStateUnload__ = &kceStateUnload_56cd7a;
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pThis->__kceRegisterIntrService__ = &kceRegisterIntrService_IMPL;
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pThis->__kceServiceNotificationInterrupt__ = &kceServiceNotificationInterrupt_IMPL;
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// Hal function -- kceGetNvlinkAutoConfigCeValues
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
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{
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pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_TU102;
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}
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else
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{
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pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_GA100;
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}
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// Hal function -- kceGetNvlinkMaxTopoForTable
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
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{
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pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_GP100;
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}
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else
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{
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pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_491d52;
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}
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// Hal function -- kceIsCurrentMaxTopology
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
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{
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pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_491d52;
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}
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else
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{
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pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_GA100;
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}
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// Hal function -- kceGetAutoConfigTableEntry
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
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{
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pThis->__kceGetAutoConfigTableEntry__ = &kceGetAutoConfigTableEntry_GH100;
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}
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else
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{
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pThis->__kceGetAutoConfigTableEntry__ = &kceGetAutoConfigTableEntry_GV100;
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}
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// Hal function -- kceGetPce2lceConfigSize1
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */
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{
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pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA100;
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}
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else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
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{
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pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GH100;
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}
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else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
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{
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pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_TU102;
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}
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else
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{
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pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA102;
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}
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// Hal function -- kceGetMappings
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
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{
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pThis->__kceGetMappings__ = &kceGetMappings_GH100;
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}
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else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
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{
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pThis->__kceGetMappings__ = &kceGetMappings_46f6a7;
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}
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else
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{
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pThis->__kceGetMappings__ = &kceGetMappings_GA100;
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}
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// Hal function -- kceMapPceLceForC2C
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
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{
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pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_GH100;
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}
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else
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{
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pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_46f6a7;
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}
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// Hal function -- kceMapPceLceForGRCE
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
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{
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pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_GH100;
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}
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// default
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else
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{
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pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_b3696a;
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}
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// Hal function -- kceMapPceLceForSysmemLinks
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */
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{
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pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA100;
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}
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else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */
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{
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pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_46f6a7;
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}
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else
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{
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pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA102;
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}
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// Hal function -- kceMapPceLceForNvlinkPeers
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
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{
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pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GH100;
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}
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else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
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{
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pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_46f6a7;
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}
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else
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{
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pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GA100;
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}
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// Hal function -- kceGetSysmemSupportedLceMask
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */
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{
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pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA100;
|
|
}
|
|
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */
|
|
{
|
|
pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_4a4dee;
|
|
}
|
|
else
|
|
{
|
|
pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA102;
|
|
}
|
|
|
|
// Hal function -- kceMapAsyncLceDefault
|
|
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
|
|
{
|
|
pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GH100;
|
|
}
|
|
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
|
|
{
|
|
pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_46f6a7;
|
|
}
|
|
else
|
|
{
|
|
pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GA100;
|
|
}
|
|
|
|
// Hal function -- kceGetNvlinkPeerSupportedLceMask
|
|
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */
|
|
{
|
|
pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA100;
|
|
}
|
|
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
|
|
{
|
|
pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_4a4dee;
|
|
}
|
|
else
|
|
{
|
|
pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA102;
|
|
}
|
|
|
|
// Hal function -- kceGetGrceSupportedLceMask
|
|
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */
|
|
{
|
|
pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA100;
|
|
}
|
|
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
|
|
{
|
|
pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_4a4dee;
|
|
}
|
|
else
|
|
{
|
|
pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA102;
|
|
}
|
|
|
|
// Hal function -- kceIsGenXorHigherSupported
|
|
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */
|
|
{
|
|
pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GA100;
|
|
}
|
|
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
|
|
{
|
|
pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GH100;
|
|
}
|
|
else
|
|
{
|
|
pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_cbe027;
|
|
}
|
|
|
|
// Hal function -- kceApplyGen4orHigherMapping
|
|
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */
|
|
{
|
|
pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_GA100;
|
|
}
|
|
else
|
|
{
|
|
pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_b3696a;
|
|
}
|
|
|
|
pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelCE_engstateConstructEngine;
|
|
|
|
pThis->__nvoc_base_OBJENGSTATE.__engstateIsPresent__ = &__nvoc_thunk_KernelCE_engstateIsPresent;
|
|
|
|
pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelCE_engstateStateLoad;
|
|
|
|
pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelCE_engstateStateUnload;
|
|
|
|
pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelCE_intrservRegisterIntrService;
|
|
|
|
pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_KernelCE_intrservServiceNotificationInterrupt;
|
|
|
|
pThis->__kceStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kceStateInitLocked;
|
|
|
|
pThis->__kceStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreLoad;
|
|
|
|
pThis->__kceStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kceStatePostUnload;
|
|
|
|
pThis->__kceStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_kceStateDestroy;
|
|
|
|
pThis->__kceStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreUnload;
|
|
|
|
pThis->__kceStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kceStateInitUnlocked;
|
|
|
|
pThis->__kceInitMissing__ = &__nvoc_thunk_OBJENGSTATE_kceInitMissing;
|
|
|
|
pThis->__kceStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreInitLocked;
|
|
|
|
pThis->__kceStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreInitUnlocked;
|
|
|
|
pThis->__kceClearInterrupt__ = &__nvoc_thunk_IntrService_kceClearInterrupt;
|
|
|
|
pThis->__kceStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kceStatePostLoad;
|
|
|
|
pThis->__kceServiceInterrupt__ = &__nvoc_thunk_IntrService_kceServiceInterrupt;
|
|
}
|
|
|
|
void __nvoc_init_funcTable_KernelCE(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) {
|
|
__nvoc_init_funcTable_KernelCE_1(pThis, pRmhalspecowner);
|
|
}
|
|
|
|
void __nvoc_init_OBJENGSTATE(OBJENGSTATE*);
|
|
void __nvoc_init_IntrService(IntrService*);
|
|
void __nvoc_init_KernelCE(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) {
|
|
pThis->__nvoc_pbase_KernelCE = pThis;
|
|
pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object;
|
|
pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE;
|
|
pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService;
|
|
__nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE);
|
|
__nvoc_init_IntrService(&pThis->__nvoc_base_IntrService);
|
|
__nvoc_init_funcTable_KernelCE(pThis, pRmhalspecowner);
|
|
}
|
|
|
|
NV_STATUS __nvoc_objCreate_KernelCE(KernelCE **ppThis, Dynamic *pParent, NvU32 createFlags) {
|
|
NV_STATUS status;
|
|
Object *pParentObj;
|
|
KernelCE *pThis;
|
|
RmHalspecOwner *pRmhalspecowner;
|
|
|
|
status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCE), (void**)&pThis, (void**)ppThis);
|
|
if (status != NV_OK)
|
|
return status;
|
|
|
|
portMemSet(pThis, 0, sizeof(KernelCE));
|
|
|
|
__nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCE);
|
|
|
|
pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags;
|
|
|
|
if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY))
|
|
{
|
|
pParentObj = dynamicCast(pParent, Object);
|
|
objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object);
|
|
}
|
|
else
|
|
{
|
|
pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL;
|
|
}
|
|
|
|
if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL)
|
|
pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent);
|
|
NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT);
|
|
|
|
__nvoc_init_KernelCE(pThis, pRmhalspecowner);
|
|
status = __nvoc_ctor_KernelCE(pThis, pRmhalspecowner);
|
|
if (status != NV_OK) goto __nvoc_objCreate_KernelCE_cleanup;
|
|
|
|
*ppThis = pThis;
|
|
|
|
return NV_OK;
|
|
|
|
__nvoc_objCreate_KernelCE_cleanup:
|
|
// do not call destructors here since the constructor already called them
|
|
if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT)
|
|
portMemSet(pThis, 0, sizeof(KernelCE));
|
|
else
|
|
portMemFree(pThis);
|
|
|
|
// coverity[leaked_storage:FALSE]
|
|
return status;
|
|
}
|
|
|
|
NV_STATUS __nvoc_objCreateDynamic_KernelCE(KernelCE **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) {
|
|
NV_STATUS status;
|
|
|
|
status = __nvoc_objCreate_KernelCE(ppThis, pParent, createFlags);
|
|
|
|
return status;
|
|
}
|
|
|