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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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177 lines
7.7 KiB
C++
177 lines
7.7 KiB
C++
/*
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* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/******************************* List **************************************\
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* *
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* Module: dp_evoadapter2x.h *
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* Interface for low level access to the aux bus for dp2x. *
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* This is the synchronous version of the interface. *
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* *
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\***************************************************************************/
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#ifndef INCLUDED_DP_EVOADAPTER2X_H
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#define INCLUDED_DP_EVOADAPTER2X_H
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#include "dp_evoadapter.h"
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#include "dp_timeout.h"
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#include "dp_linkconfig.h"
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// For channel equalization, total poll time is 450ms. Set it to 500ms for timer granularity
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#define NV_DP2X_LT_MAX_TIME_POLL_CHNL_EQ_MS (500U)
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// For channel equalization, max loop count is 20 when waiting CHANNEL_EQ_DONE set.
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#define NV_DP2X_LT_MAX_LOOP_COUNT_POLL_CHNL_EQ_DONE (20U)
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// For channel equalization, polling interval is 3 when waiting INTERLANE_ALIGN_DONE.
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#define NV_DP2X_LT_CHNL_EQ_INTERLANE_ALIGN_POLLING_INTERVAL (3U)
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// Unit definitions for Aux Read Intervals
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#define NV_DP2X_LT_CHNL_EQ_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (1U)
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#define NV_DP2X_LT_CHNL_EQ_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (2U)
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// For phase CDS, total time is (LTTPR + 1) * 20
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#define NV_DP2X_LT_MAX_POLL_TIME_CDS_MS(i) ((i+1) * 20)
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#define NV_DP2X_LT_CDS_POLLING_INTERVAL 3U
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//
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// Total possible link configurations for DP2.x fallback table.
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// Total number of link rates supported is 15:
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// 3 UHBR: UHBR20, UHBR13.5, UHBR10
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// 3 UHBR for internal test:
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// UHBR2.5, UHBR2.7, UHBR5.0
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// 4 Legacy: HBR3, HBR2, HBR, RBR
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// 5 ILR: 2.16G, 2.43G, 3.24G, 4.32G, 6.75G
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// Total number of lane count supported is 3 (1, 2, 4)
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// Total possible link configurations => 15 * 3 = 45.
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//
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#define NV_DP2X_VALID_LINK_CONFIGURATION_COUNT 45U
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namespace DisplayPort
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{
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// Simplified LinkConfiguration for fallback map
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typedef struct
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{
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NvU32 laneCount;
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// 10M unit
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LinkRate linkRate;
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//
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// The flag indicates if the link configuration is avaiable on the setup.
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// Both link count and link rate have to be supported.
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//
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bool bSupported;
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//
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// The flag indicates if the link rate can be trained with 128b/132b channel
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// coding. Default false for non-UHBR link rates.
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//
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bool bUseDP2xChannelCoding;
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} SIMPLIFIED_DP2X_LINKCONFIG;
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typedef struct
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{
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DP2X_RESET_LINK_REASON reason;
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bool bForce;
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} DP2XResetParam;
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class EvoMainLink2x : public EvoMainLink
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{
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//
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// Bit mask for GPU/DFP supported UHBR Link Rates.
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// Defines the same as NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS.UHBRSupportedByGpu and
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// NV0073_CTRL_DFP_GET_INFO_PARAMS.UHBRSupportedByDfp
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//
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NvU32 gpuUhbrCaps;
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NvU32 dfpUhbrCaps;
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bool bUseRgFlushSequence;
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bool bSupportUHBR2_50; // Support UHBR2.5 for internal testing.
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bool bSupportUHBR2_70; // Support UHBR2.7 for internal testing.
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bool bSupportUHBR5_00; // Support UHBR5.0 for internal testing.
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// Start time of DP2.x LT Channel Eqaulization phase.
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NvU64 channelEqualizationStartTimeUs;
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bool pollDP2XLinkTrainingStageDone(NvU32 stage, NvU32 laneCount,
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NvU32 phyRepeaterCount, NvU32 pollingInterval, bool force);
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//
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// Find next available link configuration in fallback mandate.
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// Return false if not available
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//
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bool getFallbackForDP2xLinkTraining(LinkConfiguration *link);
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//
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// Check if the link configuration is supported on the system,
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// and with correct channel encoding.
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// Return false if not.
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//
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bool isSupportedDPLinkConfig(LinkConfiguration &link);
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// Before link training start, reset DPRX link and make sure it's ready.
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bool resetDPRXLink(DP2XResetParam param);
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SIMPLIFIED_DP2X_LINKCONFIG fallbackMandateTable[NV_DP2X_VALID_LINK_CONFIGURATION_COUNT];
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NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS ltRmParams;
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public:
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virtual bool queryGPUCapability();
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virtual bool queryAndUpdateDfpParams();
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virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 uhbrCaps = 0);
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virtual bool configureLinkRateTable(const NvU16 *pLinkRateTable, LinkRates *pLinkRates);
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void validateIlrInFallbackMap(LinkRate ilr, bool bUseDP2xChannelCoding);
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virtual NvU32 maxLinkRateSupported();
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virtual bool setFlushMode(FlushModePhase phase);
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virtual bool clearFlushMode(FlushModePhase phase, NvU32 attachFailedHeadMask = 0, NvU32 headIndex = 0);
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virtual bool isRgFlushSequenceUsed() {return bUseRgFlushSequence;}
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void applyDP2xRegkeyOverrides();
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virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
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// Link Rate will return the value with 10M convention!
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virtual void getLinkConfig(unsigned &laneCount, NvU64 & linkRate);
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virtual NvU32 getUHBRSupported(void)
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{
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return (gpuUhbrCaps & dfpUhbrCaps);
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}
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virtual bool train(const LinkConfiguration & link, bool force,
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LinkTrainingType linkTrainingType,
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LinkConfiguration *retLink, bool bSkipLt = false,
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bool isPostLtAdjRequestGranted = false,
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unsigned phyRepeaterCount = 0);
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bool trainDP2xChannelCoding(LinkConfiguration & link, bool force,
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LinkTrainingType linkTrainingType,
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LinkConfiguration *retLink,
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bool bSkipLt, bool isPostLtAdjRequestGranted,
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unsigned phyRepeaterCount);
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EvoMainLink2x(EvoInterface *provider, Timer * timer);
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virtual bool getDp2xLaneData(NvU32 *numLanes, NvU32 *data);
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virtual bool setDp2xLaneData(NvU32 numLanes, NvU32 *data);
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virtual bool physicalLayerSetDP2xTestPattern(DP2xPatternInfo *patternInfo);
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};
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}
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#endif // INCLUDED_DP_EVOADAPTER_H
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