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42 lines
2.0 KiB
C
42 lines
2.0 KiB
C
/*
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* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _clc97d_sw_spare_h_
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#define _clc97d_sw_spare_h_
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/* This file is *not* auto-generated. */
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//
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// Quadro Sync is a mechanism used to synchronize scanout and flips between
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// GPUs in different systems (e.g., to drive large video walls, such as in a
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// planetarium). Special FPGA boards (e.g., P2060 or P2061) are added to the
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// system to provide the reference frame lock signal. The VPLL_REF field below
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// is set to "QSYNC" on the head which is selected to be driven by the external
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// reference signal. As with any HEAD_SET_SW_SPARE method, changing the value
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// of a field will trigger a supervisor interrupt sequence.
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//
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#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0
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#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000)
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#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_QSYNC (0x00000001)
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#endif // _clc97d_sw_spare_h_
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