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137 lines
6.1 KiB
C
137 lines
6.1 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __common_vgpu_mgr_h__
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#define __common_vgpu_mgr_h__
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#include "gpu/gpu.h"
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#include "gpu/fifo/kernel_fifo.h"
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#include "ctrl/ctrla081.h"
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#include "containers/list.h"
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#define MAX_VGPU_TYPES_PER_PGPU NVA081_MAX_VGPU_TYPES_PER_PGPU
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#define VGPU_CONFIG_PARAMS_MAX_LENGTH 1024
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#define VGPU_STRING_BUFFER_SIZE NVA081_VGPU_STRING_BUFFER_SIZE
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#define VGPU_UUID_SIZE NVA081_VM_UUID_SIZE
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#define VGPU_MAX_GFID 64
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#define VGPU_SIGNATURE_SIZE NVA081_VGPU_SIGNATURE_SIZE
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#define VGPU_MAX_PLUGIN_CHANNELS 5
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#define MAX_VGPU_DEVICES_PER_PGPU NVA081_MAX_VGPU_PER_PGPU
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#define SET_GUEST_ID_ACTION_SET 0
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#define SET_GUEST_ID_ACTION_UNSET 1
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typedef struct
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{
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NvU8 action;
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NvU32 vmPid;
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VM_ID_TYPE vmIdType;
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VM_ID guestVmId;
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} SET_GUEST_ID_PARAMS;
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/* This structure stores per vGPU instance supported placement information */
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typedef struct
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{
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/* For Heterogeneous vGPU mode only */
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NvU16 heterogeneousSupportedPlacementId;
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NvU16 heterogeneousSupportedChidOffset;
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/* For Homogeneous vGPU placement mode only */
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NvU16 homogeneousSupportedPlacementId;
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NvU16 homogeneousSupportedChidOffset;
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} VGPU_INSTANCE_SUPPORTED_PLACEMENT_INFO;
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/* This structure stores per vGPU type's placement information */
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typedef struct
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{
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NvU32 placementSize;
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NvU32 channelCount;
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VGPU_INSTANCE_SUPPORTED_PLACEMENT_INFO vgpuInstanceSupportedPlacementInfo[MAX_VGPU_DEVICES_PER_PGPU];
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NvU16 heterogeneousPlacementCount;
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NvU16 homogeneousPlacementCount;
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} VGPU_TYPE_SUPPORTED_PLACEMENT_INFO;
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/* This structure represents the vGPU type's attributes */
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typedef struct
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{
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NvU32 vgpuTypeId;
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NvU8 vgpuName[VGPU_STRING_BUFFER_SIZE];
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NvU8 vgpuClass[VGPU_STRING_BUFFER_SIZE];
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NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH];
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NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH];
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VGPU_TYPE_SUPPORTED_PLACEMENT_INFO vgpuTypeSupportedPlacementInfo;
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NvU32 maxInstance;
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NvU32 numHeads;
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NvU32 maxResolutionX;
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NvU32 maxResolutionY;
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NvU32 maxPixels;
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NvU32 frlConfig;
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NvU32 cudaEnabled;
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NvU32 eccSupported;
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NvU32 gpuInstanceSize;
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NvU32 multiVgpuSupported;
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NvU64 vdevId NV_ALIGN_BYTES(8);
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NvU64 pdevId NV_ALIGN_BYTES(8);
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NvU64 profileSize NV_ALIGN_BYTES(8);
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NvU64 fbLength NV_ALIGN_BYTES(8);
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NvU64 gspHeapSize NV_ALIGN_BYTES(8);
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NvU64 fbReservation NV_ALIGN_BYTES(8);
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NvU64 mappableVideoSize NV_ALIGN_BYTES(8);
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NvU32 encoderCapacity;
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NvU64 bar1Length NV_ALIGN_BYTES(8);
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NvU32 frlEnable;
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NvU32 gpuDirectSupported;
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NvU32 nvlinkP2PSupported;
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NvU32 multiVgpuExclusive;
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NvU8 vgpuExtraParams[VGPU_CONFIG_PARAMS_MAX_LENGTH];
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NvU8 vgpuSignature[VGPU_SIGNATURE_SIZE];
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} VGPU_TYPE;
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MAKE_LIST(VGPU_TYPE_LIST, VGPU_TYPE);
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void
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vgpuMgrFillVgpuType(NVA081_CTRL_VGPU_INFO *pVgpuInfo, VGPU_TYPE *pVgpuTypeNode);
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NV_STATUS
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vgpuMgrReserveSystemChannelIDs(OBJGPU *pGpu,
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VGPU_TYPE *vgpuTypeInfo,
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NvU32 gfid,
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NvU32 *pChidOffset,
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NvU32 *pChannelCount,
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Device *pMigDevice,
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NvU32 numChannels,
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NvU16 placementId,
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NvU32 engineFifoListNumEntries,
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FIFO_ENGINE_LIST *engineFifoList);
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void
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vgpuMgrFreeSystemChannelIDs(OBJGPU *pGpu,
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NvU32 gfid,
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NvU32 *pChidOffset,
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NvU32 *pChannelCount,
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Device *pMigDevice,
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NvU32 engineFifoListNumEntries,
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FIFO_ENGINE_LIST *engineFifoList);
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#endif // __common_vgpu_mgr_h__
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