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60 lines
5.3 KiB
C
60 lines
5.3 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __tu102_dev_gsp_h__
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#define __tu102_dev_gsp_h__
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#define NV_PGSP 0x113fff:0x110000 /* RW--D */
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#define NV_PGSP_FALCON_MAILBOX0 0x110040 /* RW-4R */
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#define NV_PGSP_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
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#define NV_PGSP_FALCON_MAILBOX1 0x110044 /* RW-4R */
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#define NV_PGSP_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
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#define NV_PGSP_FALCON_ENGINE 0x1103c0 /* RW-4R */
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#define NV_PGSP_FALCON_ENGINE_RESET 0:0 /* RWIVF */
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#define NV_PGSP_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
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#define NV_PGSP_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
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#define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */
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#define NV_PGSP_MAILBOX__SIZE_1 4 /* */
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#define NV_PGSP_MAILBOX_DATA 31:0 /* RWIVF */
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#define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */
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#define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */
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#define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
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#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
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#define NV_PGSP_EMEMC__SIZE_1 4 /* */
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#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */
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#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */
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#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */
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#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */
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#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
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#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */
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#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */
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#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
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#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */
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#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */
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#define NV_PGSP_EMEMD__SIZE_1 4 /* */
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#define NV_PGSP_EMEMD_DATA 31:0 /* RW-VF */
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#endif // __tu102_dev_gsp_h__
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