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374 lines
19 KiB
C
374 lines
19 KiB
C
#ifndef _G_DISP_INST_MEM_NVOC_H_
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#define _G_DISP_INST_MEM_NVOC_H_
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#include "nvoc/runtime.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "g_disp_inst_mem_nvoc.h"
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#ifndef DISPLAY_INSTANCE_MEMORY_H
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#define DISPLAY_INSTANCE_MEMORY_H
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/* ------------------------ Includes --------------------------------------- */
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#include "nvtypes.h"
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#include "nvoc/utility.h"
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#include "gpu/disp/kern_disp.h"
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#include "gpu/mem_mgr/virt_mem_allocator_common.h"
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#include "gpu/mem_mgr/mem_desc.h"
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/* ------------------------ Forward Declaration ---------------------------- */
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typedef struct OBJEHEAP OBJEHEAP;
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struct DispChannel;
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#ifndef __NVOC_CLASS_DispChannel_TYPEDEF__
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#define __NVOC_CLASS_DispChannel_TYPEDEF__
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typedef struct DispChannel DispChannel;
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#endif /* __NVOC_CLASS_DispChannel_TYPEDEF__ */
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#ifndef __nvoc_class_id_DispChannel
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#define __nvoc_class_id_DispChannel 0xbd2ff3
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#endif /* __nvoc_class_id_DispChannel */
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struct ContextDma;
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#ifndef __NVOC_CLASS_ContextDma_TYPEDEF__
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#define __NVOC_CLASS_ContextDma_TYPEDEF__
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typedef struct ContextDma ContextDma;
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#endif /* __NVOC_CLASS_ContextDma_TYPEDEF__ */
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#ifndef __nvoc_class_id_ContextDma
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#define __nvoc_class_id_ContextDma 0x88441b
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#endif /* __nvoc_class_id_ContextDma */
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/* ------------------------ Macros & Defines ------------------------------- */
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#define KERNEL_DISPLAY_GET_INST_MEM(p) ((p)->pInst)
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#define DISP_INST_MEM_ALIGN 0x10000
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/* ------------------------ Types definitions ------------------------------ */
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/*!
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* A software hash table entry
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*/
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typedef struct
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{
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struct ContextDma *pContextDma;
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struct DispChannel *pDispChannel;
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} SW_HASH_TABLE_ENTRY;
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#ifdef NVOC_DISP_INST_MEM_H_PRIVATE_ACCESS_ALLOWED
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#define PRIVATE_FIELD(x) x
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#else
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#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
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#endif
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struct DisplayInstanceMemory {
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const struct NVOC_RTTI *__nvoc_rtti;
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struct Object __nvoc_base_Object;
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struct Object *__nvoc_pbase_Object;
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struct DisplayInstanceMemory *__nvoc_pbase_DisplayInstanceMemory;
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void (*__instmemGetSize__)(OBJGPU *, struct DisplayInstanceMemory *, NvU32 *, NvU32 *);
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NvU32 (*__instmemGetHashTableBaseAddr__)(OBJGPU *, struct DisplayInstanceMemory *);
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NvBool (*__instmemIsValid__)(OBJGPU *, struct DisplayInstanceMemory *, NvU32);
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NvU32 (*__instmemGenerateHashTableData__)(OBJGPU *, struct DisplayInstanceMemory *, NvU32, NvU32, NvU32);
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NV_STATUS (*__instmemHashFunc__)(OBJGPU *, struct DisplayInstanceMemory *, NvHandle, NvHandle, NvU32, NvU32 *);
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NV_STATUS (*__instmemCommitContextDma__)(OBJGPU *, struct DisplayInstanceMemory *, struct ContextDma *);
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NV_STATUS (*__instmemUpdateContextDma__)(OBJGPU *, struct DisplayInstanceMemory *, struct ContextDma *, NvU64 *, NvU64 *, NvHandle, NvU32);
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NV_ADDRESS_SPACE instMemAddrSpace;
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NvU32 instMemAttr;
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NvU64 instMemBase;
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NvU32 instMemSize;
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MEMORY_DESCRIPTOR *pAllocedInstMemDesc;
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MEMORY_DESCRIPTOR *pInstMemDesc;
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void *pInstMem;
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NvU32 nHashTableEntries;
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NvU32 hashTableBaseAddr;
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SW_HASH_TABLE_ENTRY *pHashTable;
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OBJEHEAP *pInstHeap;
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};
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#ifndef __NVOC_CLASS_DisplayInstanceMemory_TYPEDEF__
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#define __NVOC_CLASS_DisplayInstanceMemory_TYPEDEF__
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typedef struct DisplayInstanceMemory DisplayInstanceMemory;
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#endif /* __NVOC_CLASS_DisplayInstanceMemory_TYPEDEF__ */
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#ifndef __nvoc_class_id_DisplayInstanceMemory
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#define __nvoc_class_id_DisplayInstanceMemory 0x8223e2
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#endif /* __nvoc_class_id_DisplayInstanceMemory */
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_DisplayInstanceMemory;
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#define __staticCast_DisplayInstanceMemory(pThis) \
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((pThis)->__nvoc_pbase_DisplayInstanceMemory)
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#ifdef __nvoc_disp_inst_mem_h_disabled
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#define __dynamicCast_DisplayInstanceMemory(pThis) ((DisplayInstanceMemory*)NULL)
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#else //__nvoc_disp_inst_mem_h_disabled
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#define __dynamicCast_DisplayInstanceMemory(pThis) \
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((DisplayInstanceMemory*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(DisplayInstanceMemory)))
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#endif //__nvoc_disp_inst_mem_h_disabled
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NV_STATUS __nvoc_objCreateDynamic_DisplayInstanceMemory(DisplayInstanceMemory**, Dynamic*, NvU32, va_list);
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NV_STATUS __nvoc_objCreate_DisplayInstanceMemory(DisplayInstanceMemory**, Dynamic*, NvU32);
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#define __objCreate_DisplayInstanceMemory(ppNewObj, pParent, createFlags) \
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__nvoc_objCreate_DisplayInstanceMemory((ppNewObj), staticCast((pParent), Dynamic), (createFlags))
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#define instmemGetSize(pGpu, pInstMem, pTotalInstMemSize, pHashTableSize) instmemGetSize_DISPATCH(pGpu, pInstMem, pTotalInstMemSize, pHashTableSize)
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#define instmemGetSize_HAL(pGpu, pInstMem, pTotalInstMemSize, pHashTableSize) instmemGetSize_DISPATCH(pGpu, pInstMem, pTotalInstMemSize, pHashTableSize)
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#define instmemGetHashTableBaseAddr(pGpu, pInstMem) instmemGetHashTableBaseAddr_DISPATCH(pGpu, pInstMem)
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#define instmemGetHashTableBaseAddr_HAL(pGpu, pInstMem) instmemGetHashTableBaseAddr_DISPATCH(pGpu, pInstMem)
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#define instmemIsValid(pGpu, pInstMem, offset) instmemIsValid_DISPATCH(pGpu, pInstMem, offset)
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#define instmemIsValid_HAL(pGpu, pInstMem, offset) instmemIsValid_DISPATCH(pGpu, pInstMem, offset)
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#define instmemGenerateHashTableData(pGpu, pInstMem, hClient, offset, dispChannelNum) instmemGenerateHashTableData_DISPATCH(pGpu, pInstMem, hClient, offset, dispChannelNum)
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#define instmemGenerateHashTableData_HAL(pGpu, pInstMem, hClient, offset, dispChannelNum) instmemGenerateHashTableData_DISPATCH(pGpu, pInstMem, hClient, offset, dispChannelNum)
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#define instmemHashFunc(pGpu, pInstMem, hClient, hContextDma, dispChannelNum, result) instmemHashFunc_DISPATCH(pGpu, pInstMem, hClient, hContextDma, dispChannelNum, result)
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#define instmemHashFunc_HAL(pGpu, pInstMem, hClient, hContextDma, dispChannelNum, result) instmemHashFunc_DISPATCH(pGpu, pInstMem, hClient, hContextDma, dispChannelNum, result)
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#define instmemCommitContextDma(pGpu, pInstMem, pContextDma) instmemCommitContextDma_DISPATCH(pGpu, pInstMem, pContextDma)
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#define instmemCommitContextDma_HAL(pGpu, pInstMem, pContextDma) instmemCommitContextDma_DISPATCH(pGpu, pInstMem, pContextDma)
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#define instmemUpdateContextDma(pGpu, pInstMem, pContextDma, pNewAddress, pNewLimit, hMemory, comprInfo) instmemUpdateContextDma_DISPATCH(pGpu, pInstMem, pContextDma, pNewAddress, pNewLimit, hMemory, comprInfo)
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#define instmemUpdateContextDma_HAL(pGpu, pInstMem, pContextDma, pNewAddress, pNewLimit, hMemory, comprInfo) instmemUpdateContextDma_DISPATCH(pGpu, pInstMem, pContextDma, pNewAddress, pNewLimit, hMemory, comprInfo)
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static inline void instmemDecommitContextDma_b3696a(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma) {
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return;
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}
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline void instmemDecommitContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemDecommitContextDma(pGpu, pInstMem, pContextDma) instmemDecommitContextDma_b3696a(pGpu, pInstMem, pContextDma)
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#endif //__nvoc_disp_inst_mem_h_disabled
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#define instmemDecommitContextDma_HAL(pGpu, pInstMem, pContextDma) instmemDecommitContextDma(pGpu, pInstMem, pContextDma)
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void instmemGetSize_v03_00(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *pTotalInstMemSize, NvU32 *pHashTableSize);
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static inline void instmemGetSize_f2d351(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *pTotalInstMemSize, NvU32 *pHashTableSize) {
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NV_ASSERT_PRECOMP(0);
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}
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static inline void instmemGetSize_DISPATCH(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *pTotalInstMemSize, NvU32 *pHashTableSize) {
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pInstMem->__instmemGetSize__(pGpu, pInstMem, pTotalInstMemSize, pHashTableSize);
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}
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NvU32 instmemGetHashTableBaseAddr_v03_00(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem);
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static inline NvU32 instmemGetHashTableBaseAddr_4a4dee(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem) {
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return 0;
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}
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static inline NvU32 instmemGetHashTableBaseAddr_DISPATCH(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem) {
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return pInstMem->__instmemGetHashTableBaseAddr__(pGpu, pInstMem);
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}
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NvBool instmemIsValid_v03_00(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 offset);
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static inline NvBool instmemIsValid_491d52(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 offset) {
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return ((NvBool)(0 != 0));
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}
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static inline NvBool instmemIsValid_DISPATCH(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 offset) {
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return pInstMem->__instmemIsValid__(pGpu, pInstMem, offset);
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}
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NvU32 instmemGenerateHashTableData_v03_00(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 hClient, NvU32 offset, NvU32 dispChannelNum);
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static inline NvU32 instmemGenerateHashTableData_4a4dee(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 hClient, NvU32 offset, NvU32 dispChannelNum) {
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return 0;
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}
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static inline NvU32 instmemGenerateHashTableData_DISPATCH(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 hClient, NvU32 offset, NvU32 dispChannelNum) {
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return pInstMem->__instmemGenerateHashTableData__(pGpu, pInstMem, hClient, offset, dispChannelNum);
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}
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NV_STATUS instmemHashFunc_v03_00(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvHandle hClient, NvHandle hContextDma, NvU32 dispChannelNum, NvU32 *result);
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static inline NV_STATUS instmemHashFunc_46f6a7(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvHandle hClient, NvHandle hContextDma, NvU32 dispChannelNum, NvU32 *result) {
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return NV_ERR_NOT_SUPPORTED;
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}
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static inline NV_STATUS instmemHashFunc_DISPATCH(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvHandle hClient, NvHandle hContextDma, NvU32 dispChannelNum, NvU32 *result) {
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return pInstMem->__instmemHashFunc__(pGpu, pInstMem, hClient, hContextDma, dispChannelNum, result);
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}
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NV_STATUS instmemCommitContextDma_v03_00(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma);
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static inline NV_STATUS instmemCommitContextDma_46f6a7(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma) {
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return NV_ERR_NOT_SUPPORTED;
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}
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static inline NV_STATUS instmemCommitContextDma_DISPATCH(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma) {
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return pInstMem->__instmemCommitContextDma__(pGpu, pInstMem, pContextDma);
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}
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NV_STATUS instmemUpdateContextDma_v03_00(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, NvU64 *pNewAddress, NvU64 *pNewLimit, NvHandle hMemory, NvU32 comprInfo);
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static inline NV_STATUS instmemUpdateContextDma_46f6a7(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, NvU64 *pNewAddress, NvU64 *pNewLimit, NvHandle hMemory, NvU32 comprInfo) {
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return NV_ERR_NOT_SUPPORTED;
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}
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static inline NV_STATUS instmemUpdateContextDma_DISPATCH(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, NvU64 *pNewAddress, NvU64 *pNewLimit, NvHandle hMemory, NvU32 comprInfo) {
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return pInstMem->__instmemUpdateContextDma__(pGpu, pInstMem, pContextDma, pNewAddress, pNewLimit, hMemory, comprInfo);
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}
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NV_STATUS instmemConstruct_IMPL(struct DisplayInstanceMemory *arg_pInstMem);
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#define __nvoc_instmemConstruct(arg_pInstMem) instmemConstruct_IMPL(arg_pInstMem)
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void instmemDestruct_IMPL(struct DisplayInstanceMemory *pInstMem);
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#define __nvoc_instmemDestruct(pInstMem) instmemDestruct_IMPL(pInstMem)
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NV_STATUS instmemStateInitLocked_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline NV_STATUS instmemStateInitLocked(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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return NV_ERR_NOT_SUPPORTED;
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemStateInitLocked(pGpu, pInstMem) instmemStateInitLocked_IMPL(pGpu, pInstMem)
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#endif //__nvoc_disp_inst_mem_h_disabled
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void instmemStateDestroy_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline void instmemStateDestroy(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemStateDestroy(pGpu, pInstMem) instmemStateDestroy_IMPL(pGpu, pInstMem)
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#endif //__nvoc_disp_inst_mem_h_disabled
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NV_STATUS instmemStateLoad_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 flags);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline NV_STATUS instmemStateLoad(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 flags) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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return NV_ERR_NOT_SUPPORTED;
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemStateLoad(pGpu, pInstMem, flags) instmemStateLoad_IMPL(pGpu, pInstMem, flags)
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#endif //__nvoc_disp_inst_mem_h_disabled
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NV_STATUS instmemStateUnload_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 flags);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline NV_STATUS instmemStateUnload(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 flags) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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return NV_ERR_NOT_SUPPORTED;
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemStateUnload(pGpu, pInstMem, flags) instmemStateUnload_IMPL(pGpu, pInstMem, flags)
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#endif //__nvoc_disp_inst_mem_h_disabled
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void instmemSetMemory_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NV_ADDRESS_SPACE dispInstMemAddrSpace, NvU32 dispInstMemAttr, NvU64 dispInstMemBase, NvU32 dispInstMemSize);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline void instmemSetMemory(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NV_ADDRESS_SPACE dispInstMemAddrSpace, NvU32 dispInstMemAttr, NvU64 dispInstMemBase, NvU32 dispInstMemSize) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemSetMemory(pGpu, pInstMem, dispInstMemAddrSpace, dispInstMemAttr, dispInstMemBase, dispInstMemSize) instmemSetMemory_IMPL(pGpu, pInstMem, dispInstMemAddrSpace, dispInstMemAttr, dispInstMemBase, dispInstMemSize)
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#endif //__nvoc_disp_inst_mem_h_disabled
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NV_STATUS instmemBindContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, struct DispChannel *pDispChannel);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline NV_STATUS instmemBindContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, struct DispChannel *pDispChannel) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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return NV_ERR_NOT_SUPPORTED;
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemBindContextDma(pGpu, pInstMem, pContextDma, pDispChannel) instmemBindContextDma_IMPL(pGpu, pInstMem, pContextDma, pDispChannel)
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#endif //__nvoc_disp_inst_mem_h_disabled
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NV_STATUS instmemUnbindContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, struct DispChannel *pDispChannel);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline NV_STATUS instmemUnbindContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, struct DispChannel *pDispChannel) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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return NV_ERR_NOT_SUPPORTED;
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemUnbindContextDma(pGpu, pInstMem, pContextDma, pDispChannel) instmemUnbindContextDma_IMPL(pGpu, pInstMem, pContextDma, pDispChannel)
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#endif //__nvoc_disp_inst_mem_h_disabled
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void instmemUnbindContextDmaFromAllChannels_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline void instmemUnbindContextDmaFromAllChannels(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemUnbindContextDmaFromAllChannels(pGpu, pInstMem, pContextDma) instmemUnbindContextDmaFromAllChannels_IMPL(pGpu, pInstMem, pContextDma)
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#endif //__nvoc_disp_inst_mem_h_disabled
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void instmemUnbindDispChannelContextDmas_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct DispChannel *pDispChannel);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline void instmemUnbindDispChannelContextDmas(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct DispChannel *pDispChannel) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemUnbindDispChannelContextDmas(pGpu, pInstMem, pDispChannel) instmemUnbindDispChannelContextDmas_IMPL(pGpu, pInstMem, pDispChannel)
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#endif //__nvoc_disp_inst_mem_h_disabled
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NV_STATUS instmemReserveContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *offset);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline NV_STATUS instmemReserveContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *offset) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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return NV_ERR_NOT_SUPPORTED;
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemReserveContextDma(pGpu, pInstMem, offset) instmemReserveContextDma_IMPL(pGpu, pInstMem, offset)
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#endif //__nvoc_disp_inst_mem_h_disabled
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NV_STATUS instmemFreeContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 offset);
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#ifdef __nvoc_disp_inst_mem_h_disabled
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static inline NV_STATUS instmemFreeContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 offset) {
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NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!");
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return NV_ERR_NOT_SUPPORTED;
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}
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#else //__nvoc_disp_inst_mem_h_disabled
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#define instmemFreeContextDma(pGpu, pInstMem, offset) instmemFreeContextDma_IMPL(pGpu, pInstMem, offset)
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#endif //__nvoc_disp_inst_mem_h_disabled
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#undef PRIVATE_FIELD
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#endif // DISPLAY_INSTANCE_MEMORY_H
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _G_DISP_INST_MEM_NVOC_H_
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