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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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157 lines
9.4 KiB
C
157 lines
9.4 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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//
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/***************************************************************************\
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* *
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* Hardware Reference Manual extracted defines. *
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* - Defines in this file are approved by the HW team for publishing. *
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* *
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\***************************************************************************/
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#ifndef NV_REF_PUBLISHED_H
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#define NV_REF_PUBLISHED_H
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//
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// These registers can be accessed by chip-independent code as
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// well as chip-dependent code.
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//
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// NOTE: DO NOT ADD TO THIS FILE. CREATE CHIP SPECIFIC HAL ROUTINES INSTEAD.
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//
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/*
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* Standard PCI config space header defines.
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* The defines here cannot change across generations.
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*/
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/* dev_nv_xve.ref */
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/* PBUS field defines converted to NV_CONFIG field defines */
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#define NV_CONFIG_PCI_NV_0 0x00000000 /* R--4R */
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#define NV_CONFIG_PCI_NV_0_VENDOR_ID 15:0 /* C--UF */
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#define NV_CONFIG_PCI_NV_0_VENDOR_ID_NVIDIA 0x000010DE /* C---V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID 31:16 /* R--UF */
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#define NV_CONFIG_PCI_NV_1 0x00000004 /* RW-4R */
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#define NV_CONFIG_PCI_NV_1_IO_SPACE 0:0 /* RWIVF */
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#define NV_CONFIG_PCI_NV_1_IO_SPACE_DISABLED 0x00000000 /* RWI-V */
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#define NV_CONFIG_PCI_NV_1_IO_SPACE_ENABLED 0x00000001 /* RW--V */
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#define NV_CONFIG_PCI_NV_1_MEMORY_SPACE 1:1 /* RWIVF */
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#define NV_CONFIG_PCI_NV_1_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */
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#define NV_CONFIG_PCI_NV_1_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */
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#define NV_CONFIG_PCI_NV_1_BUS_MASTER 2:2 /* RWIVF */
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#define NV_CONFIG_PCI_NV_1_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */
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#define NV_CONFIG_PCI_NV_1_BUS_MASTER_ENABLED 0x00000001 /* RW--V */
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#define NV_CONFIG_PCI_NV_2 0x00000008 /* R--4R */
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#define NV_CONFIG_PCI_NV_2_REVISION_ID 7:0 /* C--UF */
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#define NV_CONFIG_PCI_NV_2_CLASS_CODE 31:8 /* C--VF */
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#define NV_CONFIG_PCI_NV_3 0x0000000C /* RW-4R */
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#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER 15:11 /* RWIUF */
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#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_0_CLOCKS 0x00000000 /* RWI-V */
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#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_8_CLOCKS 0x00000001 /* RW--V */
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#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_240_CLOCKS 0x0000001E /* RW--V */
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#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_248_CLOCKS 0x0000001F /* RW--V */
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#define NV_CONFIG_PCI_NV_4 0x00000010 /* RW-4R */
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#define NV_CONFIG_PCI_NV_5 0x00000014 /* RW-4R */
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#define NV_CONFIG_PCI_NV_5_ADDRESS_TYPE 2:1 /* C--VF */
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#define NV_CONFIG_PCI_NV_5_ADDRESS_TYPE_64_BIT 0x00000002 /* ----V */
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#define NV_CONFIG_PCI_NV_6 0x00000018 /* RW-4R */
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#define NV_CONFIG_PCI_NV_7(i) (0x0000001C+(i)*4) /* R--4A */
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#define NV_CONFIG_PCI_NV_11 0x0000002C /* R--4R */
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#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_VENDOR_ID 15:0 /* R--UF */
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#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R---V */
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#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID 31:16 /* R--UF */
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#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID_NONE 0x00000000 /* R---V */
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#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID_TNT2PRO 0x0000001f
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#define NV_CONFIG_PCI_NV_12 0x00000030 /* RW-4R */
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#define NV_CONFIG_PCI_NV_13 0x00000034 /* RW-4R */
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#define NV_CONFIG_PCI_NV_13_CAP_PTR 7:0 /* C--VF */
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#define NV_CONFIG_PCI_NV_14 0x00000038 /* R--4R */
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#define NV_CONFIG_PCI_NV_15 0x0000003C /* RW-4R */
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#define NV_CONFIG_PCI_NV_15_INTR_LINE 7:0 /* RWIVF */
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/*
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* These defines are the correct fields to be used to extract the
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* NEXT_PTR and CAP_ID from any PCI capability structure,
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* but they still have NV_24 in the name because they were from the
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* first PCI capability structure in the capability list in older GPUs.
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*/
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#define NV_CONFIG_PCI_NV_24_NEXT_PTR 15:8 /* R--VF */
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#define NV_CONFIG_PCI_NV_24_CAP_ID 7:0 /* C--VF */
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/*
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* Standard registers present on NVIDIA chips used to ID the chip.
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* Very stable across generations.
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*/
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/* dev_master.ref */
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#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
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#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* R--VF */
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#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* R--VF */
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#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 /* R--VF */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_0 0x00000000 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_1 0x00000001 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_2 0x00000002 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_3 0x00000003 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_4 0x00000004 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_5 0x00000005 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_6 0x00000006 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_7 0x00000007 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_8 0x00000008 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_9 0x00000009 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_A 0x0000000A /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0x0000000B /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_C 0x0000000C /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_D 0x0000000D /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_E 0x0000000E /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_F 0x0000000F /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 /* R--VF */
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#define NV_PMC_BOOT_0_ARCHITECTURE_TU100 0x00000016 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_TU110 0x00000016 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 0x00000017 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GH100 0x00000018 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_AD100 0x00000019 /* R---V */
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#define NV_PMC_BOOT_1 0x00000004 /* R--4R */
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#define NV_PMC_BOOT_1_VGPU8 8:8 /* R--VF */
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#define NV_PMC_BOOT_1_VGPU8_REAL 0x00000000 /* R-I-V */
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#define NV_PMC_BOOT_1_VGPU8_VIRTUAL 0x00000001 /* R---V */
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#define NV_PMC_BOOT_1_VGPU16 16:16 /* R--VF */
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#define NV_PMC_BOOT_1_VGPU16_REAL 0x00000000 /* R-I-V */
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#define NV_PMC_BOOT_1_VGPU16_VIRTUAL 0x00000001 /* R---V */
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#define NV_PMC_BOOT_1_VGPU 17:16 /* C--VF */
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#define NV_PMC_BOOT_1_VGPU_REAL 0x00000000 /* C---V */
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#define NV_PMC_BOOT_1_VGPU_PV 0x00000001 /* ----V */
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#define NV_PMC_BOOT_1_VGPU_VF 0x00000002 /* ----V */
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#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */
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#define NV_PMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */
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#define NV_PMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */
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#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */
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#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
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/* dev_arapb_misc.h */
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#define NV_PAPB_MISC_GP_HIDREV_CHIPID 15:8 /* ----F */
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#define NV_PAPB_MISC_GP_HIDREV_MAJORREV 7:4 /* ----F */
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#endif // NV_REF_PUBLISHED_H
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