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275 lines
12 KiB
C
275 lines
12 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrl0080/ctrl0080gr.finn
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//
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#include "ctrl/ctrl0080/ctrl0080base.h"
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typedef struct NV0080_CTRL_GR_ROUTE_INFO {
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NvU32 flags;
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NV_DECLARE_ALIGNED(NvU64 route, 8);
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} NV0080_CTRL_GR_ROUTE_INFO;
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/* NV01_DEVICE_XX/NV03_DEVICE gr engine control commands and parameters */
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/**
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* NV0080_CTRL_CMD_GR_GET_CAPS
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*
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* This command returns the set of graphics capabilities for the device
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* in the form of an array of unsigned bytes. Graphics capabilities
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* include supported features and required workarounds for the graphics
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* engine(s) within the device, each represented by a byte offset into the
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* table and a bit position within that byte.
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*
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* capsTblSize
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* This parameter specifies the size in bytes of the caps table.
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* This value should be set to NV0080_CTRL_GR_CAPS_TBL_SIZE.
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* capsTbl
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* This parameter specifies a pointer to the client's caps table buffer
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* into which the graphics caps bits will be transferred by the RM.
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* The caps table is an array of unsigned bytes.
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*/
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#define NV0080_CTRL_CMD_GR_GET_CAPS (0x801102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x2U)
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typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS {
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NvU32 capsTblSize;
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NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
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} NV0080_CTRL_GR_GET_CAPS_PARAMS;
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/* extract cap bit setting from tbl */
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#define NV0080_CTRL_GR_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
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/*
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* Size in bytes of gr caps table. This value should be one greater
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* than the largest byte_index value above.
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*/
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#define NV0080_CTRL_GR_CAPS_TBL_SIZE 23
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/*
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* NV0080_CTRL_CMD_GR_INFO
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*
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* This structure represents a single 32bit graphics engine value. Clients
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* request a particular graphics engine value by specifying a unique bus
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* information index.
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*
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* Legal graphics information index values are:
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* NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
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* This index is used to request the number of clip IDs supported by
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* the device.
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* NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
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* This index is used to request the minimum number of attributes that
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* need to be enabled to avoid bug 261894. A return value of 0
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* indicates that there is no minimum and the bug is not present on this
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* system.
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*/
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typedef struct NV0080_CTRL_GR_INFO {
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NvU32 index;
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NvU32 data;
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} NV0080_CTRL_GR_INFO;
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/* valid graphics info index values */
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#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000)
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#define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 (0x00000001)
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#define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK (0x00000002)
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#define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT (0x00000003)
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#define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT (0x00000004)
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#define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE (0x00000005)
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#define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT (0x00000006)
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#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT (0x00000007)
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#define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR (0x00000008)
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#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT (0x00000009)
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#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT (0x0000000A)
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#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT (0x0000000B)
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#define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION (0x0000000C)
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#define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM (0x0000000D)
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#define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP (0x0000000E)
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#define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES (0x0000000F)
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#define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES (0x00000010)
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#define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY (0x00000011)
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#define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY (0x00000012)
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#define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM (0x00000013)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS (0x00000014)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS (0x00000015)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS (0x00000016)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC (0x00000017)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS (0x00000018)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS (0x00000019)
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#define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED (0x0000001A)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS (0x0000001B)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC (0x0000001C)
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#define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT (0x0000001D)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES (0x0000001E)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS (0x0000001F)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC (0x00000020)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS (0x00000021)
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#define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT (0x00000022)
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#define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT (0x00000023)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS (0x00000024)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS (0x00000025)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES (0x00000026)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC (0x00000027)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP (0x00000028)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC (0x00000029)
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#define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC (0x0000002A)
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#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP (0x0000002B)
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#define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT (0x0000002C)
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#define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT (0x0000002D)
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#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E)
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/* When adding a new INDEX, please update MAX_SIZE accordingly
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* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
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* reflects that.
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*/
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#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000031)
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#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x32) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
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/*
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* NV0080_CTRL_CMD_GR_GET_INFO
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*
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* This command returns graphics engine information for the associate GPU.
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* Request to retrieve graphics information use a list of one or more
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* NV0080_CTRL_GR_INFO structures.
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*
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* grInfoListSize
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* This field specifies the number of entries on the caller's
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* grInfoList.
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* grInfoList
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* This field specifies a pointer in the caller's address space
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* to the buffer into which the bus information is to be returned.
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* This buffer must be at least as big as grInfoListSize multiplied
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* by the size of the NV0080_CTRL_GR_INFO structure.
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*/
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#define NV0080_CTRL_CMD_GR_GET_INFO (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x4U)
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typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS {
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NvU32 grInfoListSize;
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NV_DECLARE_ALIGNED(NvP64 grInfoList, 8);
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} NV0080_CTRL_GR_GET_INFO_PARAMS;
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/*
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* NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE
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* This command gets the current partition mode of a TSG context.
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*
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* NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE
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* This command sets the partition mode of a TSG context.
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*
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* NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
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* This structure defines the parameters used for TPC partitioning mode SET/GET commands
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*
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* hChannelGroup [IN]
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* RM Handle to the TSG
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*
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* mode [IN/OUT]
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* Partitioning mode enum value
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* For the SET cmd, this is an input parameter
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* For the GET cmd, this is an output parameter
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*
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* bEnableAllTpcs [IN]
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* Flag to enable all TPCs by default
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*
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* grRouteInfo[IN]
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* This parameter specifies the routing information used to
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* disambiguate the target GR engine.
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*
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*/
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#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */
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#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */
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/* Enum for listing TPC partitioning modes */
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typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE {
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NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0,
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NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1,
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NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2,
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} NV0080_CTRL_GR_TPC_PARTITION_MODE;
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typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS {
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NvHandle hChannelGroup; // [in]
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NV0080_CTRL_GR_TPC_PARTITION_MODE mode; // [in/out]
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NvBool bEnableAllTpcs; // [in/out]
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NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in]
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} NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS;
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/**
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* NV0080_CTRL_CMD_GR_GET_CAPS_V2
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*
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* This command returns the same set of graphics capabilities for the device
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* as @ref NV0080_CTRL_CMD_GR_GET_CAPS. The difference is in the structure
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* NV0080_CTRL_GR_GET_INFO_V2_PARAMS, which contains a statically sized array,
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* rather than a caps table pointer and a caps table size in
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* NV0080_CTRL_GR_GET_INFO_PARAMS. Additionally,
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* NV0080_CTRL_GR_GET_INFO_V2_PARAMS contains a parameter for specifying routing
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* information, used for MIG.
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*
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* capsTbl
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* This parameter specifies a pointer to the client's caps table buffer
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* into which the graphics caps bits will be written by the RM.
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* The caps table is an array of unsigned bytes.
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*
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* grRouteInfo
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* This parameter specifies the routing information used to
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* disambiguate the target GR engine.
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*
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* bCapsPopulated
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* This parameter indicates that the capsTbl has been partially populated by
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* previous calls to NV0080_CTRL_CMD_GR_GET_CAPS_V2 on other subdevices.
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*/
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#define NV0080_CTRL_CMD_GR_GET_CAPS_V2 (0x801109) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U)
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typedef struct NV0080_CTRL_GR_GET_CAPS_V2_PARAMS {
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NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE];
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NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
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NvBool bCapsPopulated;
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} NV0080_CTRL_GR_GET_CAPS_V2_PARAMS;
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#define NV0080_CTRL_CMD_GR_GET_INFO_V2 (0x801110) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U)
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typedef struct NV0080_CTRL_GR_GET_INFO_V2_PARAMS {
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NvU32 grInfoListSize;
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NV0080_CTRL_GR_INFO grInfoList[NV0080_CTRL_GR_INFO_MAX_SIZE];
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NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
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} NV0080_CTRL_GR_GET_INFO_V2_PARAMS;
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/* _ctrl0080gr_h_ */
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