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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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166 lines
8.0 KiB
C
166 lines
8.0 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef ENGINE_IDX_H
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#define ENGINE_IDX_H
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#include "utils/nvbitvector.h"
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/***************************************************************************\
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* *
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* Module: engine_idx.h
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* List of engines for use by INTR (and MC) modules.
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* *
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\***************************************************************************/
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//
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// Engine bits for use by various MC HAL routines
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//
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#define MC_ENGINE_IDX_NULL 0 // This must be 0
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#define MC_ENGINE_IDX_TMR 1
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#define MC_ENGINE_IDX_DISP 2
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#define MC_ENGINE_IDX_FB 3
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#define MC_ENGINE_IDX_FIFO 4
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#define MC_ENGINE_IDX_VIDEO 5
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#define MC_ENGINE_IDX_MD 6
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#define MC_ENGINE_IDX_BUS 7
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// UNUSED
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#define MC_ENGINE_IDX_PMGR 9
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#define MC_ENGINE_IDX_VP2 10
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#define MC_ENGINE_IDX_CIPHER 11
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#define MC_ENGINE_IDX_BIF 12
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#define MC_ENGINE_IDX_PPP 13
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#define MC_ENGINE_IDX_PRIVRING 14
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#define MC_ENGINE_IDX_PMU 15
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#define MC_ENGINE_IDX_CE0 16
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#define MC_ENGINE_IDX_CE1 17
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#define MC_ENGINE_IDX_CE2 18
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#define MC_ENGINE_IDX_CE3 19
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#define MC_ENGINE_IDX_CE4 20
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#define MC_ENGINE_IDX_CE5 21
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#define MC_ENGINE_IDX_CE6 22
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#define MC_ENGINE_IDX_CE7 23
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#define MC_ENGINE_IDX_CE8 24
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#define MC_ENGINE_IDX_CE9 25
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#define MC_ENGINE_IDX_VIC 26
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#define MC_ENGINE_IDX_ISOHUB 27
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#define MC_ENGINE_IDX_VGPU 28
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#define MC_ENGINE_IDX_MSENC 29
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#define MC_ENGINE_IDX_MSENC1 30
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#define MC_ENGINE_IDX_MSENC2 31
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#define MC_ENGINE_IDX_C2C 32
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// UNUSED
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#define MC_ENGINE_IDX_LTC 34
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#define MC_ENGINE_IDX_FBHUB 35
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#define MC_ENGINE_IDX_HDACODEC 36
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#define MC_ENGINE_IDX_GMMU 37
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#define MC_ENGINE_IDX_SEC2 38
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#define MC_ENGINE_IDX_FSP 39
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#define MC_ENGINE_IDX_NVLINK 40
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#define MC_ENGINE_IDX_GSP 41
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#define MC_ENGINE_IDX_NVJPG 42
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#define MC_ENGINE_IDX_NVJPEG MC_ENGINE_IDX_NVJPG
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#define MC_ENGINE_IDX_NVJPEG0 MC_ENGINE_IDX_NVJPEG
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#define MC_ENGINE_IDX_NVJPEG1 43
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#define MC_ENGINE_IDX_NVJPEG2 44
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#define MC_ENGINE_IDX_NVJPEG3 45
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#define MC_ENGINE_IDX_NVJPEG4 46
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#define MC_ENGINE_IDX_NVJPEG5 47
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#define MC_ENGINE_IDX_NVJPEG6 48
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#define MC_ENGINE_IDX_NVJPEG7 49
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#define MC_ENGINE_IDX_REPLAYABLE_FAULT 50
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#define MC_ENGINE_IDX_ACCESS_CNTR 51
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#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 52
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#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR 53
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#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR 54
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#define MC_ENGINE_IDX_INFO_FAULT 55
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#define MC_ENGINE_IDX_BSP 56
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#define MC_ENGINE_IDX_NVDEC MC_ENGINE_IDX_BSP
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#define MC_ENGINE_IDX_NVDEC0 MC_ENGINE_IDX_NVDEC
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#define MC_ENGINE_IDX_NVDEC1 57
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#define MC_ENGINE_IDX_NVDEC2 58
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#define MC_ENGINE_IDX_NVDEC3 59
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#define MC_ENGINE_IDX_NVDEC4 60
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#define MC_ENGINE_IDX_NVDEC5 61
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#define MC_ENGINE_IDX_NVDEC6 62
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#define MC_ENGINE_IDX_NVDEC7 63
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#define MC_ENGINE_IDX_CPU_DOORBELL 64
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#define MC_ENGINE_IDX_PRIV_DOORBELL 65
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#define MC_ENGINE_IDX_MMU_ECC_ERROR 66
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#define MC_ENGINE_IDX_BLG 67
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#define MC_ENGINE_IDX_PERFMON 68
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#define MC_ENGINE_IDX_BUF_RESET 69
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#define MC_ENGINE_IDX_XBAR 70
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#define MC_ENGINE_IDX_ZPW 71
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#define MC_ENGINE_IDX_OFA0 72
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#define MC_ENGINE_IDX_TEGRA 73
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#define MC_ENGINE_IDX_GR 74
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#define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR
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#define MC_ENGINE_IDX_GR1 75
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#define MC_ENGINE_IDX_GR2 76
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#define MC_ENGINE_IDX_GR3 77
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#define MC_ENGINE_IDX_GR4 78
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#define MC_ENGINE_IDX_GR5 79
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#define MC_ENGINE_IDX_GR6 80
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#define MC_ENGINE_IDX_GR7 81
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#define MC_ENGINE_IDX_ESCHED 82
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#define MC_ENGINE_IDX_ESCHED__SIZE 64
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#define MC_ENGINE_IDX_GR_FECS_LOG 146
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#define MC_ENGINE_IDX_GR0_FECS_LOG MC_ENGINE_IDX_GR_FECS_LOG
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#define MC_ENGINE_IDX_GR1_FECS_LOG 147
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#define MC_ENGINE_IDX_GR2_FECS_LOG 148
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#define MC_ENGINE_IDX_GR3_FECS_LOG 149
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#define MC_ENGINE_IDX_GR4_FECS_LOG 150
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#define MC_ENGINE_IDX_GR5_FECS_LOG 151
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#define MC_ENGINE_IDX_GR6_FECS_LOG 152
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#define MC_ENGINE_IDX_GR7_FECS_LOG 153
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#define MC_ENGINE_IDX_TMR_SWRL 154
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#define MC_ENGINE_IDX_MAX 155 // This must be kept as the max bit if
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// we need to add more engines
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#define MC_ENGINE_IDX_INVALID 0xFFFFFFFF
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// Index GR reference
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#define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x))
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#define MC_ENGINE_IDX_GRn_FECS_LOG(x) (MC_ENGINE_IDX_GR0_FECS_LOG + (x))
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// Index CE reference
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#define MC_ENGINE_IDX_CE(x) (MC_ENGINE_IDX_CE0 + (x))
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// Index MSENC reference
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#define MC_ENGINE_IDX_MSENCn(x) (MC_ENGINE_IDX_MSENC + (x))
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// Index NVDEC reference
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#define MC_ENGINE_IDX_NVDECn(x) (MC_ENGINE_IDX_NVDEC + (x))
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// Index NVJPEG reference
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#define MC_ENGINE_IDX_NVJPEGn(x) (MC_ENGINE_IDX_NVJPEG + (x))
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// Index ESCHED reference
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#define MC_ENGINE_IDX_ESCHEDn(x) (MC_ENGINE_IDX_ESCHED + (x))
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MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX);
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typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR;
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#endif // ENGINE_IDX_H
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