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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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237 lines
11 KiB
C
237 lines
11 KiB
C
#ifndef _G_IOACCESS_NVOC_H_
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#define _G_IOACCESS_NVOC_H_
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#include "nvoc/runtime.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH)
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#include "g_ioaccess_nvoc.h"
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#endif
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#ifndef _IO_ACCESS_H_
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#define _IO_ACCESS_H_
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#include "nvtypes.h"
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#include "nvstatus.h"
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#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH)
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#include "nvoc/prelude.h"
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#endif
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#define REG_DRF_SHIFT(drf) ((0?drf) % 32)
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#define REG_DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32)))
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#define REG_DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<<REG_DRF_SHIFT(NV ## d ## r ## f))
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#define REG_DRF_NUM(d,r,f,n) (((n)®_DRF_MASK(NV ## d ## r ## f))<<REG_DRF_SHIFT(NV ## d ## r ## f))
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#define REG_DRF_VAL(d,r,f,v) (((v)>>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f))
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#define REG_DRF_SHIFTMASK(drf) (REG_DRF_MASK(drf)<<(REG_DRF_SHIFT(drf)))
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#define REG_DRF_WIDTH(drf) ((1?drf) - (0?drf) + 1)
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#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH)
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#define REG_RD08(ap, addr) regaprtReadReg08 (staticCast(ap, RegisterAperture), addr)
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#define REG_RD16(ap, addr) regaprtReadReg16 (staticCast(ap, RegisterAperture), addr)
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#define REG_RD32(ap, addr) regaprtReadReg32 (staticCast(ap, RegisterAperture), addr)
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#define REG_WR08(ap, addr, val) regaprtWriteReg08 (staticCast(ap, RegisterAperture), addr, val)
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#define REG_WR16(ap, addr, val) regaprtWriteReg16 (staticCast(ap, RegisterAperture), addr, val)
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#define REG_WR32(ap, addr, val) regaprtWriteReg32 (staticCast(ap, RegisterAperture), addr, val)
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#define REG_WR32_UC(ap, addr, val) regaprtWriteReg32Uc(staticCast(ap, RegisterAperture), addr, val)
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#define REG_VALID(ap, addr) regaprtIsRegValid (staticCast(ap, RegisterAperture), addr)
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#ifdef NVOC_IOACCESS_H_PRIVATE_ACCESS_ALLOWED
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#define PRIVATE_FIELD(x) x
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#else
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#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
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#endif
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struct RegisterAperture {
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const struct NVOC_RTTI *__nvoc_rtti;
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struct RegisterAperture *__nvoc_pbase_RegisterAperture;
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NvU8 (*__regaprtReadReg08__)(struct RegisterAperture *, NvU32);
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NvU16 (*__regaprtReadReg16__)(struct RegisterAperture *, NvU32);
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NvU32 (*__regaprtReadReg32__)(struct RegisterAperture *, NvU32);
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void (*__regaprtWriteReg08__)(struct RegisterAperture *, NvU32, NvV8);
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void (*__regaprtWriteReg16__)(struct RegisterAperture *, NvU32, NvV16);
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void (*__regaprtWriteReg32__)(struct RegisterAperture *, NvU32, NvV32);
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void (*__regaprtWriteReg32Uc__)(struct RegisterAperture *, NvU32, NvV32);
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NvBool (*__regaprtIsRegValid__)(struct RegisterAperture *, NvU32);
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};
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#ifndef __NVOC_CLASS_RegisterAperture_TYPEDEF__
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#define __NVOC_CLASS_RegisterAperture_TYPEDEF__
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typedef struct RegisterAperture RegisterAperture;
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#endif /* __NVOC_CLASS_RegisterAperture_TYPEDEF__ */
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#ifndef __nvoc_class_id_RegisterAperture
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#define __nvoc_class_id_RegisterAperture 0xfcaf2e
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#endif /* __nvoc_class_id_RegisterAperture */
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture;
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#define __staticCast_RegisterAperture(pThis) \
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((pThis)->__nvoc_pbase_RegisterAperture)
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#ifdef __nvoc_ioaccess_h_disabled
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#define __dynamicCast_RegisterAperture(pThis) ((RegisterAperture*)NULL)
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#else //__nvoc_ioaccess_h_disabled
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#define __dynamicCast_RegisterAperture(pThis) \
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((RegisterAperture*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(RegisterAperture)))
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#endif //__nvoc_ioaccess_h_disabled
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NV_STATUS __nvoc_objCreateDynamic_RegisterAperture(RegisterAperture**, Dynamic*, NvU32, va_list);
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NV_STATUS __nvoc_objCreate_RegisterAperture(RegisterAperture**, Dynamic*, NvU32);
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#define __objCreate_RegisterAperture(ppNewObj, pParent, createFlags) \
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__nvoc_objCreate_RegisterAperture((ppNewObj), staticCast((pParent), Dynamic), (createFlags))
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#define regaprtReadReg08(pAperture, addr) regaprtReadReg08_DISPATCH(pAperture, addr)
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#define regaprtReadReg16(pAperture, addr) regaprtReadReg16_DISPATCH(pAperture, addr)
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#define regaprtReadReg32(pAperture, addr) regaprtReadReg32_DISPATCH(pAperture, addr)
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#define regaprtWriteReg08(pAperture, addr, value) regaprtWriteReg08_DISPATCH(pAperture, addr, value)
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#define regaprtWriteReg16(pAperture, addr, value) regaprtWriteReg16_DISPATCH(pAperture, addr, value)
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#define regaprtWriteReg32(pAperture, addr, value) regaprtWriteReg32_DISPATCH(pAperture, addr, value)
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#define regaprtWriteReg32Uc(pAperture, addr, value) regaprtWriteReg32Uc_DISPATCH(pAperture, addr, value)
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#define regaprtIsRegValid(pAperture, addr) regaprtIsRegValid_DISPATCH(pAperture, addr)
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static inline NvU8 regaprtReadReg08_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) {
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return pAperture->__regaprtReadReg08__(pAperture, addr);
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}
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static inline NvU16 regaprtReadReg16_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) {
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return pAperture->__regaprtReadReg16__(pAperture, addr);
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}
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static inline NvU32 regaprtReadReg32_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) {
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return pAperture->__regaprtReadReg32__(pAperture, addr);
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}
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static inline void regaprtWriteReg08_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV8 value) {
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pAperture->__regaprtWriteReg08__(pAperture, addr, value);
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}
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static inline void regaprtWriteReg16_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV16 value) {
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pAperture->__regaprtWriteReg16__(pAperture, addr, value);
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}
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static inline void regaprtWriteReg32_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) {
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pAperture->__regaprtWriteReg32__(pAperture, addr, value);
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}
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static inline void regaprtWriteReg32Uc_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) {
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pAperture->__regaprtWriteReg32Uc__(pAperture, addr, value);
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}
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static inline NvBool regaprtIsRegValid_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) {
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return pAperture->__regaprtIsRegValid__(pAperture, addr);
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}
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#undef PRIVATE_FIELD
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//
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// TODO: Remove the wrapper structure WAR once NVOC supports in-place object construction
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// The proxy structure was introduced to avoid major refactoring until the feature is implemented
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// Also fix IoAperture getters
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// Use the interface class in NVWATCH once NVOC is enabled there
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//
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#else // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH)
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typedef struct IO_DEVICE IO_DEVICE;
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typedef struct IO_APERTURE IO_APERTURE;
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typedef NvU8 ReadReg008Fn(IO_APERTURE *a, NvU32 addr);
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typedef NvU16 ReadReg016Fn(IO_APERTURE *a, NvU32 addr);
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typedef NvU32 ReadReg032Fn(IO_APERTURE *a, NvU32 addr);
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typedef void WriteReg008Fn(IO_APERTURE *a, NvU32 addr, NvV8 value);
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typedef void WriteReg016Fn(IO_APERTURE *a, NvU32 addr, NvV16 value);
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typedef void WriteReg032Fn(IO_APERTURE *a, NvU32 addr, NvV32 value);
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typedef NvBool ValidRegFn(IO_APERTURE *a, NvU32 addr);
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#define REG_RD08(ap, addr) (ap)->pDevice->pReadReg008Fn((ap), (addr))
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#define REG_RD16(ap, addr) (ap)->pDevice->pReadReg016Fn((ap), (addr))
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#define REG_RD32(ap, addr) (ap)->pDevice->pReadReg032Fn((ap), (addr))
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#define REG_WR08(ap, addr, val) (ap)->pDevice->pWriteReg008Fn((ap), (addr), (val))
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#define REG_WR16(ap, addr, val) (ap)->pDevice->pWriteReg016Fn((ap), (addr), (val))
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#define REG_WR32(ap, addr, val) (ap)->pDevice->pWriteReg032Fn((ap), (addr), (val))
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#define REG_WR32_UC(ap, addr, val) (ap)->pDevice->pWriteReg032UcFn((ap), (addr), (val))
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#define REG_VALID(ap, addr) (ap)->pDevice->pValidRegFn((ap), (addr))
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// Get the address of a register given the Aperture and offset.
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#define REG_GET_ADDR(ap, offset) ((ap)->baseAddress + (offset))
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struct IO_DEVICE
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{
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ReadReg008Fn *pReadReg008Fn;
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ReadReg016Fn *pReadReg016Fn;
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ReadReg032Fn *pReadReg032Fn;
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WriteReg008Fn *pWriteReg008Fn;
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WriteReg016Fn *pWriteReg016Fn;
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WriteReg032Fn *pWriteReg032Fn;
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WriteReg032Fn *pWriteReg032UcFn;
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ValidRegFn *pValidRegFn;
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};
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struct IO_APERTURE
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{
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IO_DEVICE *pDevice; // Pointer to module specific IO_DEVICE
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NvU32 baseAddress; // register base address
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NvU32 length; // length of aperture
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};
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NV_STATUS ioaccessInitIOAperture
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(
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IO_APERTURE *pAperture,
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IO_APERTURE *pParentAperture,
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IO_DEVICE *pDevice,
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NvU32 offset,
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NvU32 length
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);
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#endif // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH)
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//
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// Macros for register I/O
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//
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#define REG_FLD_WR_DRF_NUM(ap,d,r,f,n) REG_WR32(ap,NV##d##r,(REG_RD32(ap,NV##d##r)&~(REG_DRF_MASK(NV##d##r##f)<<REG_DRF_SHIFT(NV##d##r##f)))|REG_DRF_NUM(d,r,f,n))
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#define REG_FLD_WR_DRF_DEF(ap,d,r,f,c) REG_WR32(ap,NV##d##r,(REG_RD32(ap,NV##d##r)&~(REG_DRF_MASK(NV##d##r##f)<<REG_DRF_SHIFT(NV##d##r##f)))|REG_DRF_DEF(d,r,f,c))
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#define REG_RD_DRF(ap,d,r,f) (((REG_RD32(ap,NV ## d ## r))>>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f))
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#define REG_FLD_TEST_DRF_DEF(ap,d,r,f,c) (REG_RD_DRF(ap,d, r, f) == NV##d##r##f##c)
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#define REG_FLD_TEST_DRF_NUM(ap,d,r,f,n) (REG_RD_DRF(ap,d, r, f) == n)
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#define REG_FLD_IDX_TEST_DRF_DEF(ap,d,r,f,c,i) (REG_IDX_RD_DRF(ap, d, r, i, f) == NV##d##r##f##c)
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// Read/write a field or entire register of which there are several copies each accessed via an index
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#define REG_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV ## d ## r(i), REG_DRF_NUM(d,r,f,n))
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#define REG_IDX_WR_DRF_DEF(ap,d,r,i,f,c) REG_WR32(ap,NV ## d ## r(i), REG_DRF_DEF(d,r,f,c))
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#define REG_FLD_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV##d##r(i),(REG_RD32(ap,NV##d##r(i))&~(REG_DRF_MASK(NV##d##r##f)<<REG_DRF_SHIFT(NV##d##r##f)))|REG_DRF_NUM(d,r,f,n))
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#define REG_FLD_IDX_WR_DRF_DEF(ap,d,r,i,f,c) REG_WR32(ap,NV##d##r(i),(REG_RD32(ap,NV##d##r(i))&~(REG_DRF_MASK(NV##d##r##f)<<REG_DRF_SHIFT(NV##d##r##f)))|REG_DRF_DEF(d,r,f,c))
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#define REG_IDX_RD_DRF(ap,d,r,i,f) (((REG_RD32(ap,NV ## d ## r(i)))>>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f))
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#define REG_RD_DRF_IDX(ap,d,r,f,i) (((REG_RD32(ap,NV ## d ## r))>>REG_DRF_SHIFT(NV ## d ## r ## f(i)))®_DRF_MASK(NV ## d ## r ## f(i)))
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#define REG_IDX_OFFSET_RD_DRF(ap,d,r,i,o,f) (((REG_RD32(ap,NV ## d ## r(i,o)))>>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f))
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#endif // _IO_ACCESS_H_
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _G_IOACCESS_NVOC_H_
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