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590 lines
23 KiB
C
590 lines
23 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrl0080/ctrl0080gpu.finn
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//
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#include "ctrl/ctrl0080/ctrl0080base.h"
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#include "nvlimits.h"
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/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */
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/*
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* NV0080_CTRL_CMD_GPU_GET_CLASSLIST
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*
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* This command returns supported class information for the specified device.
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* If the device is comprised of more than one GPU, the class list represents
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* the set of supported classes common to all GPUs within the device.
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*
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* It has two modes:
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*
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* If the classList pointer is NULL, then this command returns the number
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* of classes supported by the device in the numClasses field. The value
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* should then be used by the client to allocate a classList buffer
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* large enough to hold one 32bit value per numClasses entry.
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*
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* If the classList pointer is non-NULL, then this command returns the
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* set of supported class numbers in the specified buffer.
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*
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* numClasses
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* If classList is NULL, then this parameter will return the
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* number of classes supported by the device. If classList is non-NULL,
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* then this parameter indicates the number of entries in classList.
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* classList
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* This parameter specifies a pointer to the client's buffer into
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* which the supported class numbers should be returned.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_OPERATING_SYSTEM
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*/
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#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST (0x800201) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x1U)
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typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS {
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NvU32 numClasses;
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NV_DECLARE_ALIGNED(NvP64 classList, 8);
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} NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS;
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/**
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* NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES
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*
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* This command returns the number of subdevices for the device.
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*
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* numSubDevices
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* This parameter returns the number of subdevices within the device.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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*/
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#define NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES (0x800280) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID (0x80U)
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typedef struct NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS {
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NvU32 numSubDevices;
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} NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS;
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/*
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* NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER
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*
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* This command returns the video link order of each subdevice id inside the
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* device. This call can only be made after SLI is enabled. This call is
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* intended for 3D clients to use to determine the vidlink order of the
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* devices. The Display Output Parent will always be the first subdevice
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* mask listed in the array. Note that this command should not be used in
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* case of bridgeless SLI. The order of the subdevices returned by this
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* command will not be correct in case of bridgeless SLI.
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*
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* ConnectionCount
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* Each HW can provide 1 or 2 links between all GPUs in a device. This
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* number tells how many links are available between GPUs. This data
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* also represents the number of concurrent SLI heads that can run at
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* the same time over this one device.
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*
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* Order
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* This array returns the order of subdevices that are used through
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* the vidlink for display output.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_PARAM_STRUCT
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*/
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#define NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER (0x800281) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID (0x81U)
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typedef struct NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS {
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NvU32 ConnectionCount;
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NvU32 Order[NV_MAX_SUBDEVICES];
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} NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS;
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/*
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* NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER
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*
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* This command sets display ownership within the device to the specified
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* subdevice instance. The actual transfer of display ownership will take
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* place at the next modeset.
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*
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* subDeviceInstance
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* This member specifies the subdevice instance of the new display
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* owner. The subdevice instance must be in the legal range
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* indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INVALID_PARAM_STRUCT
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*/
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#define NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER (0x800282) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x82U)
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typedef struct NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS {
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NvU32 subDeviceInstance;
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} NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS;
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/*
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* NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER
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*
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* This command returns the subdevice instance of the current display owner
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* within the device.
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*
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* subDeviceInstance
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* This member returns the subdevice instance of the current display
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* owner. The subdevice instance will be in the legal range
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* indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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*/
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#define NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER (0x800283) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x83U)
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typedef struct NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS {
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NvU32 subDeviceInstance;
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} NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS;
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/*
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* NV0080_CTRL_CMD_GPU_SET_VIDLINK
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*
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* This command enables or disables the VIDLINK of all subdevices in the
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* current SLI configuration.
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*
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* enable
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* Enables or disables the vidlink
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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*/
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#define NV0080_CTRL_CMD_GPU_SET_VIDLINK (0x800285) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID (0x85U)
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typedef struct NV0080_CTRL_GPU_SET_VIDLINK_PARAMS {
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NvU32 enable;
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} NV0080_CTRL_GPU_SET_VIDLINK_PARAMS;
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#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE (0x00000000)
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#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE (0x00000001)
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/* commands */
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#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS 0
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#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN 1
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#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP 2
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/* status */
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#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON 0
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#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN 1
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#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED 2
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#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP 3
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/*
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* NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE
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*
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* This command is used to enable or disable the persistence of a GPU's
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* software state when no clients exist. With persistent software state enabled
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* the GPU's software state is not torn down when the last client exits, but is
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* retained until either the kernel module unloads or persistent software state
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* is disabled.
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*
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* newState
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* This input parameter is used to enable or disable the persistence of the
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* software state of all subdevices within the device.
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* Possible values are:
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* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED
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* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE (0x800287) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */
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/* Possible values of persistentSwState */
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#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED (0x00000000)
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#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED (0x00000001)
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#define NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x87U)
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typedef struct NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS {
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NvU32 newState;
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} NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS;
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/*
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* NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE
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*
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* swStatePersistence
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* This parameter returns a value indicating if persistent software
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* state is currently enabled or not for the specified GPU. See the
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* description of NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE.
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* Possible values are:
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* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED
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* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE (0x800288) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x88U)
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typedef struct NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS {
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NvU32 swStatePersistence;
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} NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS;
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/**
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* NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE
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*
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* This command returns a value indicating virtualization mode in
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* which the GPU is running.
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*
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* virtualizationMode
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* This parameter returns the virtualization mode of the device.
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* Possible values are:
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* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE
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* This value indicates that there is no virtualization mode associated with the
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* device (i.e. it's a baremetal GPU).
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* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS
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* This value indicates that the device is associated with the NMOS.
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* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX
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* This value indicates that the device is associated with VGX(guest GPU).
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* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
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* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU
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* This value indicates that the device is associated with vGPU(host GPU).
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* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA
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* This value indicates that the device is associated with vSGA(host GPU).
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE (0x800289) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE (0x00000000)
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#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS (0x00000001)
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#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX (0x00000002)
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#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST (0x00000003)
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#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
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#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA (0x00000004)
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#define NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID (0x89U)
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typedef struct NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS {
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NvU32 virtualizationMode;
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} NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS;
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/*
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* NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE
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*
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* This command returns the setting information for sparse texture compute
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* mode optimization on the associated GPU. This setting indicates how the
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* large page size should be selected by the RM for the GPU.
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*
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* defaultSetting
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* This field specifies what the OS default setting is for the associated
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* GPU. See NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list
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* of possible values.
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* currentSetting
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* This field specifies which optimization mode was applied when the
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* driver was loaded. See
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* NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of
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* possible values.
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* pendingSetting
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* This field specifies which optimization mode will be applied on the
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* next driver reload. See
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* NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of
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* possible values.
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8CU)
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typedef struct NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS {
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NvU32 defaultSetting;
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NvU32 currentSetting;
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NvU32 pendingSetting;
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} NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS;
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/*
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* NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE
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*
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* This command sets the pending setting for sparse texture compute mode. This
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* setting indicates how the large page size should be selected by the RM for
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* the GPU on the next driver reload.
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*
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* setting
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* This field specifies which use case the RM should optimize the large
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* page size for on the next driver reload. Possible values for this
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* field are:
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* NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT
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* This value indicates that the RM should use the default setting for
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* the GPU's large page size. The default setting is reported by
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* NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE.
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* NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE
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* This value indicates that the RM should select the GPU's large page
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* size to optimize for compute use cases.
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* NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE
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* This value indicates that the RM should select the GPU's large page
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* size to optimize for sparse texture use cases.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_INSUFFICIENT_PERMISSIONS
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*/
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#define NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8DU)
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typedef struct NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS {
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NvU32 setting;
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} NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS;
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/* Possible sparse texture compute mode setting values */
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#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT 0
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#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE 1
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#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE 2
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/*
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* NV0080_CTRL_CMD_GPU_GET_VGX_CAPS
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*
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* This command gets the VGX capability of the GPU depending on the status of
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* the VGX hardware fuse.
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*
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* isVgx
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* This field is set to NV_TRUE is VGX fuse is enabled for the GPU otherwise
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* it is set to NV_FALSE.
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*
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* Possible status values returned are:
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* NVOS_STATUS_SUCCESS
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* NVOS_STATUS_ERROR_NOT_SUPPORTED
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*/
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#define NV0080_CTRL_CMD_GPU_GET_VGX_CAPS (0x80028e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID (0x8EU)
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typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS {
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NvBool isVgx;
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} NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS;
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/*
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* NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS
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*
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* This command is used to query GPU SRIOV capabilities
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* totalVFs
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* Total number of virtual functions supported.
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*
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* firstVfOffset
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* Offset of the first VF.
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*
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* vfFeatureMask
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* Bitmask of features managed by the guest
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*
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* FirstVFBar0Address
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* Address of BAR0 region of first VF.
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*
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* FirstVFBar1Address
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* Address of BAR1 region of first VF.
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*
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* FirstVFBar2Address
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* Address of BAR2 region of first VF.
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*
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* bar0Size
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* Size of BAR0 region on VF.
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*
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* bar1Size
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* Size of BAR1 region on VF.
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*
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* bar2Size
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* Size of BAR2 region on VF.
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*
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* b64bitBar0
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* If the VF BAR0 is 64-bit addressable.
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*
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* b64bitBar1
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* If the VF BAR1 is 64-bit addressable.
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*
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* b64bitBar2
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* If the VF BAR2 is 64-bit addressable.
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*
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* bSriovEnabled
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* Flag for SR-IOV enabled or not.
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*
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* bSriovHeavyEnabled
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* Flag for whether SR-IOV is enabled in standard or heavy mode.
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*
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* bEmulateVFBar0TlbInvalidationRegister
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* Flag for whether VF's TLB Invalidate Register region needs emulation.
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*
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* bClientRmAllocatedCtxBuffer
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* Flag for whether engine ctx buffer is managed by client RM.
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*
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* bNonPowerOf2ChannelCountSupported
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* Flag for whether non power of 2 VF channels are supported.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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*/
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#define NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS (0x800291) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID (0x91U)
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typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
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NvU32 totalVFs;
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NvU32 firstVfOffset;
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NvU32 vfFeatureMask;
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NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8);
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NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8);
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NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8);
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NV_DECLARE_ALIGNED(NvU64 bar0Size, 8);
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NV_DECLARE_ALIGNED(NvU64 bar1Size, 8);
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NV_DECLARE_ALIGNED(NvU64 bar2Size, 8);
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NvBool b64bitBar0;
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NvBool b64bitBar1;
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NvBool b64bitBar2;
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NvBool bSriovEnabled;
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NvBool bSriovHeavyEnabled;
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NvBool bEmulateVFBar0TlbInvalidationRegister;
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NvBool bClientRmAllocatedCtxBuffer;
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NvBool bNonPowerOf2ChannelCountSupported;
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} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS;
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// Update this macro if new HW exceeds GPU Classlist MAX_SIZE
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#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 160
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#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID (0x92U)
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typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS {
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NvU32 numClasses; // __OUT__
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NvU32 classList[NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE]; // __OUT__
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} NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS;
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/*
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* NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE
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*
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* Find a subdevice handle allocated under this device
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*/
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#define NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE (0x800293) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID (0x93U)
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typedef struct NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM {
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NvU32 subDeviceInst; // [in]
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NvHandle hSubDevice; // [out]
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} NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM;
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/*
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* NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS
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*
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* This command gets branding information for the device.
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*
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* brands
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* Mask containing branding information. A bit in this
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* mask is set if the GPU has particular branding.
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO NVBIT(0)
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#define NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS NVBIT(1)
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#define NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN NVBIT(2)
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#define NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS (0x800294) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID (0x94U)
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typedef struct NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS {
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NvU32 brands;
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} NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS;
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/*
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* These are the per-VF BAR1 sizes that we support in MB.
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* They are used with the NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE control call and
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* should match the NV_XVE_BAR1_CONFIG_SIZE register defines.
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*/
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M 64
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M 128
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M 256
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M 512
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G 1024
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G 2048
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G 4096
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G 8192
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G 16384
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G 32768
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G 65536
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G 131072
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M
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#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G
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#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID NV_U32_MAX
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/*
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* NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE
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*
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* @brief Resize BAR1 per-VF on the given GPU
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* vfBar1SizeMB[in] size of per-VF BAR1 size in MB
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* numVfs[out] number of VFs that can be created given the new BAR1 size
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*/
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#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE (0x800296) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID" */
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#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID (0x96U)
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typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
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NvU32 vfBar1SizeMB;
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NvU32 numVfs;
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} NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS;
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/* _ctrl0080gpu_h_ */
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