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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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262 lines
12 KiB
C++
262 lines
12 KiB
C++
/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/******************************* List **************************************\
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* *
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* Module: dp_mainlink.h *
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* Mainlink interface implemented by client. *
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* *
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\***************************************************************************/
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#ifndef INCLUDED_DP_MAINLINK_H
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#define INCLUDED_DP_MAINLINK_H
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#include "dp_linkconfig.h"
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#include "dp_vrr.h"
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#include "dp_wardatabase.h"
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#include "dp_auxdefs.h"
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#include "displayport.h"
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#include "ctrl/ctrl0073/ctrl0073dp.h"
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#include "dp_regkeydatabase.h"
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#define HDCP_DUMMY_CN (0x1)
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#define HDCP_DUMMY_CKSV (0xFFFFF)
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namespace DisplayPort
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{
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typedef enum
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{
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NONE, //Abort it manually
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UNTRUST, //Abort due to Kp mismatch
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UNRELBL, //Abort due to repeated link failure
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KSV_LEN, //Abort due to KSV length
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KSV_SIG, //Abort due to KSV signature
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SRM_SIG, //Abort due to SRM signature
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SRM_REV, //Abort due to SRM revocation
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NORDY, //Abort due to repeater not ready
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KSVTOP, //Abort due to KSV topology error
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BADBKSV //Abort due to invalid Bksv
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}AbortAuthReason;
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// This is also used for DPCD offset 10B. 249
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enum LinkQualityPatternType
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{
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LINK_QUAL_DISABLED,
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LINK_QUAL_D10_2,
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LINK_QUAL_SYM_ERROR,
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LINK_QUAL_PRBS7,
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LINK_QUAL_80BIT_CUST,
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LINK_QUAL_HBR2_COMPLIANCE_EYE,
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LINK_QUAL_CP2520PAT3,
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};
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typedef struct
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{
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LinkQualityPatternType lqsPattern;
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//
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// 80 bits DP CSTM Test Pattern data;
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// ctsmLower takes bits 31:0 (lowest 32 bits)
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// ctsmMiddle takes bits 63:32 (middle 32 bits)
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// ctsmUpper takes bits 79:64 (highest 16 bits)
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//
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int ctsmLower;
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int ctsmMiddle;
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int ctsmUpper;
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} PatternInfo;
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typedef struct
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{
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unsigned char bcaps;
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unsigned char bksv[5];
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bool hdcpCapable;
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unsigned char updMask;
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}RmDfpCache;
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typedef enum
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{
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NORMAL_LINK_TRAINING, // full LT
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NO_LINK_TRAINING,
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FAST_LINK_TRAINING,
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}LinkTrainingType;
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class MainLink : virtual public Object
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{
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public:
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virtual bool physicalLayerSetTestPattern(PatternInfo * patternInfo) = 0;
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//
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// Wrappers for existing link training RM control calls
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//
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virtual bool train(const LinkConfiguration & link, bool force, LinkTrainingType linkTrainingType,
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LinkConfiguration *retLink, bool bSkipLt = false, bool isPostLtAdjRequestGranted = false,
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unsigned phyRepeaterCount = 0) = 0;
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// RM control call to retrieve buffer from RM for DP Library to dump logs
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virtual bool retrieveRingBuffer(NvU8 dpRingBuffertype, NvU32 numRecords) = 0;
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//
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// Requests to DD to perform pre & post link training steps
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// which may disconnect and later reconnect the head (For Pre-gf119 GPUs)
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//
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virtual void preLinkTraining(NvU32 head) = 0;
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virtual void postLinkTraining(NvU32 head) = 0;
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virtual NvU32 getRegkeyValue(const char *key) = 0;
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virtual const DP_REGKEY_DATABASE& getRegkeyDatabase() = 0;
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virtual NvU32 getSorIndex() = 0;
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virtual bool isInbandStereoSignalingSupported() = 0;
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virtual bool isEDP() = 0;
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virtual bool supportMSAOverMST() = 0;
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virtual bool isForceRmEdidRequired() = 0;
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virtual bool fetchEdidByRmCtrl(NvU8* edidBuffer, NvU32 bufferSize) = 0;
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virtual bool applyEdidOverrideByRmCtrl(NvU8* edidBuffer, NvU32 bufferSize) = 0;
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// Return if Panel is Dynamic MUX capable
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virtual bool isDynamicMuxCapable() = 0;
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// Return the current mux state. Returns false if not mux capable
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virtual bool getDynamicMuxState(NvU32 *muxState) = 0;
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// Return if Internal panel is Dynamic Mux capable
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virtual bool isInternalPanelDynamicMuxCapable() = 0;
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// Check if we should skip power down eDP when head detached.
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virtual bool skipPowerdownEdpPanelWhenHeadDetach() = 0;
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// Get GPU DSC capabilities
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virtual void getDscCaps(bool *pbDscSupported = NULL,
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unsigned *pEncoderColorFormatMask = NULL,
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unsigned *pLineBufferSizeKB = NULL,
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unsigned *pRateBufferSizeKB = NULL,
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unsigned *pBitsPerPixelPrecision = NULL,
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unsigned *pMaxNumHztSlices = NULL,
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unsigned *pLineBufferBitDepth = NULL) = 0;
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//
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// Get the current link config.
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// (Used for the boot case where EFI/VBIOS may have already trained
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// the link. We need this to confirm the programming since
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// we cannot rely on the DPCD registers being correct or sane)
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//
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virtual void getLinkConfig(unsigned &laneCount, NvU64 & linkRate) = 0;
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// Get the max link config from UEFI.
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virtual bool getMaxLinkConfigFromUefi(NvU8 &linkRate, NvU8 &laneCount) = 0;
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//
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// Query if a head is attached to this DisplayId
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//
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virtual bool isActive() = 0;
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virtual bool hasIncreasedWatermarkLimits() = 0;
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virtual bool hasMultistream() = 0;
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virtual bool isPC2Disabled() = 0;
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virtual NvU32 getGpuDpSupportedVersions() = 0;
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virtual bool isStreamCloningEnabled() = 0;
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virtual NvU32 maxLinkRateSupported() = 0;
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virtual bool isLttprSupported() = 0;
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virtual bool isFECSupported() = 0;
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virtual bool setDpMSAParameters(bool bStereoEnable, const NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS &msaparams) = 0;
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virtual bool setDpStereoMSAParameters(bool bStereoEnable, const NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS &msaparams) = 0;
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virtual bool setFlushMode() = 0;
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virtual void clearFlushMode(unsigned headMask, bool testMode=false) = 0;
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//
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// HDCP Renegotiate and trigger ACT.
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//
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virtual void configureHDCPRenegotiate(NvU64 cN = HDCP_DUMMY_CN, NvU64 cKsv = HDCP_DUMMY_CKSV, bool bForceReAuth = false, bool bRxIDMsgPending = false) = 0;
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virtual void triggerACT() = 0;
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virtual void configureHDCPGetHDCPState(HDCPState &hdcpState) = 0;
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virtual NvU32 streamToHead(NvU32 streamId,
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DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY) = 0;
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virtual NvU32 headToStream(NvU32 head,
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DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY) = 0;
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virtual void configureSingleStream(NvU32 head,
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NvU32 hBlankSym,
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NvU32 vBlankSym,
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bool bEnhancedFraming,
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NvU32 tuSize,
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NvU32 waterMark,
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DP_COLORFORMAT colorFormat,
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DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamId = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY,
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DP_SINGLE_HEAD_MULTI_STREAM_MODE singleHeadMultistreamMode = DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE,
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bool bEnableAudioOverRightPanel = false,
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bool bEnable2Head1Or = false)= 0;
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virtual void configureMultiStream(NvU32 head,
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NvU32 hBlankSym,
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NvU32 vBlankSym,
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NvU32 slotStart,
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NvU32 slotEnd,
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NvU32 PBN,
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NvU32 Timeslice,
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DP_COLORFORMAT colorFormat,
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DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY,
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DP_SINGLE_HEAD_MULTI_STREAM_MODE singleHeadMultistreamMode = DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE,
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bool bEnableAudioOverRightPanel = false,
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bool bEnable2Head1Or = false)= 0;
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virtual void configureSingleHeadMultiStreamMode(NvU32 displayIDs[],
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NvU32 numStreams,
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NvU32 mode,
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bool bSetConfig,
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NvU8 vbiosPrimaryDispIdIndex = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY)= 0;
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virtual void configureMsScratchRegisters(NvU32 address,
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NvU32 hopCount,
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NvU32 driverState) = 0;
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virtual bool controlRateGoverning(NvU32 head, bool enable, bool updateNow = true) = 0;
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virtual bool getDpTestPattern(NV0073_CTRL_DP_TESTPATTERN * testPattern) = 0;
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virtual bool setDpTestPattern(NV0073_CTRL_DP_TESTPATTERN testPattern,
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NvU8 laneMask, NV0073_CTRL_DP_CSTM cstm,
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NvBool bIsHBR2, NvBool bSkipLaneDataOverride = false) = 0;
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virtual bool getDpLaneData(NvU32 *numLanes, NvU32 *data) = 0;
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virtual bool setDpLaneData(NvU32 numLanes, NvU32 *data) = 0;
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virtual bool rmUpdateDynamicDfpCache(NvU32 headIndex, RmDfpCache * dfpCache, NvBool bResetDfp) = 0;
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virtual void configurePowerState(bool bPowerUp) = 0;
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virtual NvU32 monitorDenylistInfo(NvU32 ManufacturerID, NvU32 ProductID, DpMonitorDenylistData *pDenylistData) = 0;
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virtual NvU32 getRootDisplayId() = 0;
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virtual NvU32 allocDisplayId() = 0;
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virtual bool freeDisplayId(NvU32 displayId) = 0;
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virtual void queryGPUCapability() = 0;
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virtual bool queryAndUpdateDfpParams() = 0;
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virtual bool getEdpPowerData(bool *panelPowerOn, bool *bDPCDPowerStateD0) = 0;
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virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status) = 0;
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virtual void configureTriggerSelect(NvU32 head,
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DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY) = 0;
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virtual void configureTriggerAll(NvU32 head, bool enable) = 0;
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virtual bool dscCrcTransaction(NvBool bEnable, gpuDscCrc *data, NvU16 *headIndex){ return false; }
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virtual bool configureLinkRateTable(const NvU16 *pLinkRateTable, LinkRates *pLinkRates) = 0;
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virtual bool configureFec(const bool bEnableFec) = 0;
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};
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}
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#endif //INCLUDED_DP_MAINLINK_H
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