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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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650 lines
21 KiB
C
650 lines
21 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DISPLAYPORT_H_
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#define _DISPLAYPORT_H_
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#include "nvmisc.h"
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#include "dpcd.h"
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#include "dpcd14.h"
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#include "dpcd20.h"
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/**************** Resource Manager Defines and Structures ******************\
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* *
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* Module: DISPLAYPORT.H *
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* Defines DISPLAYPORT V1.2 *
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* *
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\***************************************************************************/
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// Displayport interoperability with HDMI dongle i2c addr
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#define DP2HDMI_DONGLE_I2C_ADDR 0x80
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#define DP2HDMI_DONGLE_DDC_BUFFER_ID_LEN 16
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#define DP2HDMI_DONGLE_CAP_BUFFER_LEN 32
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// Offset to read the dongle identifier
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#define NV_DP2HDMI_DONGLE_IDENTIFIER (0x00000010)
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#define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_REV 2:0
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#define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_REV_TYPE2 (0x00000000)
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#define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_ID 7:4
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#define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_ID_TYPE2 (0x0000000A)
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// Offset to read the dongle TMDS clock rate
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#define NV_DP2HDMI_DONGLE_TMDS_CLOCK_RATE (0x0000001D)
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// HDMI dongle types
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#define DP2HDMI_DONGLE_TYPE_1 0x1
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#define DP2HDMI_DONGLE_TYPE_2 0x2
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// HDMI dongle frequency limits
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#define DP2HDMI_DONGLE_TYPE_1_PCLK_LIMIT 165*1000*1000
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#define DP2HDMI_DONGLE_TYPE_2_PCLK_LIMIT 300*1000*1000
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#define DPCD_VERSION_12 0x12
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#define DPCD_VERSION_13 0x13
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#define DPCD_VERSION_14 0x14
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#define DP_LINKINDEX_0 0x0
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#define DP_LINKINDEX_1 0x1
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// Two Head One OR
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#define NV_PRIMARY_HEAD_INDEX_0 0
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#define NV_SECONDARY_HEAD_INDEX_1 1
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#define NV_PRIMARY_HEAD_INDEX_2 2
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#define NV_SECONDARY_HEAD_INDEX_3 3
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typedef enum
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{
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displayPort_Lane0 = 0,
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displayPort_Lane1 = 1,
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displayPort_Lane2 = 2,
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displayPort_Lane3 = 3,
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displayPort_Lane4 = 4,
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displayPort_Lane5 = 5,
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displayPort_Lane6 = 6,
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displayPort_Lane7 = 7,
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displayPort_LaneSupported
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} DP_LANE;
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typedef enum
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{
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laneCount_0 = 0x0,
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laneCount_1 = 0x1,
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laneCount_2 = 0x2,
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laneCount_4 = 0x4,
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laneCount_8 = 0x8,
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laneCount_Supported
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} DP_LANE_COUNT;
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typedef enum
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{
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// enum value unit = 270M
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linkBW_1_62Gbps = 0x06,
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linkBW_2_16Gbps = 0x08,
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linkBW_2_43Gbps = 0x09,
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linkBW_2_70Gbps = 0x0A,
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linkBW_3_24Gbps = 0x0C,
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linkBW_4_32Gbps = 0x10,
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linkBW_5_40Gbps = 0x14,
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linkBW_8_10Gbps = 0x1E,
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linkBW_Supported
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} DP_LINK_BANDWIDTH;
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typedef enum
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{
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linkSpeedId_1_62Gbps = 0x00,
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linkSpeedId_2_70Gbps = 0x01,
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linkSpeedId_5_40Gbps = 0x02,
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linkSpeedId_8_10Gbps = 0x03,
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linkSpeedId_2_16Gbps = 0x04,
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linkSpeedId_2_43Gbps = 0x05,
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linkSpeedId_3_24Gbps = 0x06,
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linkSpeedId_4_32Gbps = 0x07,
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linkSpeedId_Supported
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} DP_LINK_SPEED_INDEX;
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typedef enum
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{
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postCursor2_Level0 = 0,
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postCursor2_Level1 = 1,
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postCursor2_Level2 = 2,
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postCursor2_Level3 = 3,
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postCursor2_Supported
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} DP_POSTCURSOR2;
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typedef enum
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{
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preEmphasis_Disabled = 0,
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preEmphasis_Level1 = 1,
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preEmphasis_Level2 = 2,
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preEmphasis_Level3 = 3,
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preEmphasis_Supported
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} DP_PREEMPHASIS;
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typedef enum
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{
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driveCurrent_Level0 = 0,
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driveCurrent_Level1 = 1,
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driveCurrent_Level2 = 2,
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driveCurrent_Level3 = 3,
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driveCurrent_Supported
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} DP_DRIVECURRENT;
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typedef enum
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{
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trainingPattern_Disabled = 0x0,
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trainingPattern_1 = 0x1,
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trainingPattern_2 = 0x2,
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trainingPattern_3 = 0x3,
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trainingPattern_4 = 0xB
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} DP_TRAININGPATTERN;
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typedef enum
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{
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dpOverclock_Percentage_0 = 0,
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dpOverclock_Percentage_10 = 10,
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dpOverclock_Percentage_20 = 20
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}DP_OVERCLOCKPERCENTAGE;
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typedef enum
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{
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dpColorFormat_RGB = 0,
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dpColorFormat_YCbCr444 = 0x1,
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dpColorFormat_YCbCr422 = 0x2,
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dpColorFormat_YCbCr420 = 0x3,
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dpColorFormat_Unknown = 0xF
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} DP_COLORFORMAT;
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typedef enum
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{
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dp_pktType_VideoStreamconfig = 0x7,
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dp_pktType_CeaHdrMetaData = 0x21,
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dp_pktType_SRInfoFrame = 0x7f, // Self refresh infoframe for eDP enter/exit self refresh, SRS 1698
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dp_pktType_Cea861BInfoFrame = 0x80,
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dp_pktType_VendorSpecInfoFrame = 0x81,
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dp_pktType_AviInfoFrame = 0x82,
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dp_pktType_AudioInfoFrame = 0x84,
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dp_pktType_SrcProdDescInfoFrame = 0x83,
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dp_pktType_MpegSrcInfoFrame = 0x85,
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dp_pktType_DynamicRangeMasteringInfoFrame = 0x87
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} DP_PACKET_TYPE;
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typedef enum
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{
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DSC_SLICES_PER_SINK_1 = 1,
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DSC_SLICES_PER_SINK_2 = 2,
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DSC_SLICES_PER_SINK_4 = 4,
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DSC_SLICES_PER_SINK_6 = 6,
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DSC_SLICES_PER_SINK_8 = 8,
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DSC_SLICES_PER_SINK_10 = 10,
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DSC_SLICES_PER_SINK_12 = 12,
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DSC_SLICES_PER_SINK_16 = 16,
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DSC_SLICES_PER_SINK_20 = 20,
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DSC_SLICES_PER_SINK_24 = 24
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} DscSliceCount;
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typedef enum
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{
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DSC_BITS_PER_COLOR_MASK_8 = 1,
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DSC_BITS_PER_COLOR_MASK_10 = 2,
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DSC_BITS_PER_COLOR_MASK_12 = 4
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}DscBitsPerColorMask;
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enum DSC_MODE
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{
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DSC_SINGLE,
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DSC_DUAL,
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DSC_DROP,
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DSC_MODE_NONE
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};
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typedef enum
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{
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BITS_PER_PIXEL_PRECISION_1_16 = 0,
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BITS_PER_PIXEL_PRECISION_1_8 = 1,
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BITS_PER_PIXEL_PRECISION_1_4 = 2,
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BITS_PER_PIXEL_PRECISION_1_2 = 3,
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BITS_PER_PIXEL_PRECISION_1 = 4
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}BITS_PER_PIXEL_INCREMENT;
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typedef enum
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{
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NV_DP_FEC_UNCORRECTED = 0,
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NV_DP_FEC_CORRECTED = 1,
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NV_DP_FEC_BIT = 2,
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NV_DP_FEC_PARITY_BLOCK = 3,
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NV_DP_FEC_PARITY_BIT = 4
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}FEC_ERROR_COUNTER;
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typedef struct DscCaps
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{
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NvBool bDSCSupported;
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NvBool bDSCDecompressionSupported;
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NvBool bDSCPassThroughSupported;
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unsigned versionMajor, versionMinor;
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unsigned rcBufferBlockSize;
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unsigned rcBuffersize;
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unsigned maxSlicesPerSink;
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unsigned lineBufferBitDepth;
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NvBool bDscBlockPredictionSupport;
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unsigned maxBitsPerPixelX16;
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unsigned sliceCountSupportedMask;
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struct
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{
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NvBool bRgb;
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NvBool bYCbCr444;
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NvBool bYCbCrSimple422;
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NvBool bYCbCrNative422;
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NvBool bYCbCrNative420;
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}dscDecoderColorFormatCaps;
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unsigned dscDecoderColorDepthMask;
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unsigned dscPeakThroughputMode0;
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unsigned dscPeakThroughputMode1;
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unsigned dscMaxSliceWidth;
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unsigned branchDSCOverallThroughputMode0;
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unsigned branchDSCOverallThroughputMode1;
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unsigned branchDSCMaximumLineBufferWidth;
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BITS_PER_PIXEL_INCREMENT dscBitsPerPixelIncrement;
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} DscCaps;
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typedef struct GpuDscCrc
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{
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NvU16 gpuCrc0;
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NvU16 gpuCrc1;
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NvU16 gpuCrc2;
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} gpuDscCrc;
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typedef struct SinkDscCrc
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{
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NvU16 sinkCrc0;
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NvU16 sinkCrc1;
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NvU16 sinkCrc2;
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} sinkDscCrc;
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typedef struct
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{
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NvBool bSourceControlModeSupported;
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NvBool bConcurrentLTSupported;
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NvBool bConv444To420Supported;
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NvU32 maxTmdsClkRate;
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NvU8 maxBpc;
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NvU8 maxHdmiLinkBandwidthGbps;
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} PCONCaps;
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typedef enum
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{
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PCON_HDMI_LINK_BW_FRL_9GBPS = 0,
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PCON_HDMI_LINK_BW_FRL_18GBPS,
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PCON_HDMI_LINK_BW_FRL_24GBPS,
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PCON_HDMI_LINK_BW_FRL_32GBPS,
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PCON_HDMI_LINK_BW_FRL_40GBPS,
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PCON_HDMI_LINK_BW_FRL_48GBPS,
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PCON_HDMI_LINK_BW_FRL_INVALID
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} PCONHdmiLinkBw;
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typedef enum
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{
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NV_DP_PCON_CONTROL_STATUS_SUCCESS = 0,
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NV_DP_PCON_CONTROL_STATUS_ERROR_TIMEOUT = 0x80000001,
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NV_DP_PCON_CONTROL_STATUS_ERROR_FRL_LT_FAILURE = 0x80000002,
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NV_DP_PCON_CONTROL_STATUS_ERROR_FRL_NOT_SUPPORTED = 0x80000003,
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NV_DP_PCON_CONTROL_STATUS_ERROR_GENERIC = 0x8000000F
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} NV_DP_PCON_CONTROL_STATUS;
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//
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// Poll HDMI-Link Status change and FRL Ready.
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// Spec says it should be done in 500ms, we give it 20% extra time:
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// 60 times with interval 10ms.
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//
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#define NV_PCON_SOURCE_CONTROL_MODE_TIMEOUT_THRESHOLD (60)
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#define NV_PCON_SOURCE_CONTROL_MODE_TIMEOUT_INTERVAL_MS (10)
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//
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// Poll HDMI-Link Status change IRQ and Link Status.
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// Spec says it should be done in 250ms, we give it 20% extra time:
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// 30 times with interval 10ms.
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//
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#define NV_PCON_FRL_LT_TIMEOUT_THRESHOLD (30)
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#define NV_PCON_FRL_LT_TIMEOUT_INTERVAL_MS (10)
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typedef struct _PCONLinkControl
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{
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struct
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{
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// This struct is being passed in for assessPCONLink I/F
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NvU32 bAssessLink : 1;
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// Specify if client wants to use src control - set it false DPLib can just do DP LT alone.
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// By default it should be true.
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NvU32 bSourceControlMode : 1;
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// Default is sequential mode, set this to choose concurrent mode
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NvU32 bConcurrentMode : 1;
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// Default is normal link training mode (stop once FRL-LT succeed).
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// Set this to link train all requested FRL Bw in allowedFrlBwMask.
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NvU32 bExtendedLTMode : 1;
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// Keep PCON links (DP and FRL link) alive
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NvU32 bKeepPCONLinkAlive : 1;
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// Default DPLib will fallback to autonomous mode and perform DP assessLink.
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NvU32 bSkipFallback : 1;
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} flags;
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// Input: Clients use this to specify the FRL BW PCON should try.
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NvU32 frlHdmiBwMask;
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struct
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{
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NV_DP_PCON_CONTROL_STATUS status;
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PCONHdmiLinkBw maxFrlBwTrained;
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NvU32 trainedFrlBwMask;
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} result;
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} PCONLinkControl;
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static NV_INLINE PCONHdmiLinkBw getMaxFrlBwFromMask(NvU32 frlRateMask)
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{
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if (frlRateMask == 0)
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{
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// Nothing is set. Assume TMDS
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return PCON_HDMI_LINK_BW_FRL_INVALID;
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}
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// find highest set bit (destructive operation)
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HIGHESTBITIDX_32(frlRateMask);
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return (PCONHdmiLinkBw)frlRateMask;
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}
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/*
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EDP VESA PSR defines
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*/
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// PSR state transitions
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typedef enum
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{
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vesaPsrStatus_Inactive = 0,
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vesaPsrStatus_Transition2Active = 1,
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vesaPsrStatus_DisplayFromRfb = 2,
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vesaPsrStatus_CaptureAndDisplay = 3,
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vesaPsrStatus_Transition2Inactive = 4,
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vesaPsrStatus_Undefined5 = 5,
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vesaPsrStatus_Undefined6 = 6,
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vesaPsrStatus_SinkError = 7
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} vesaPsrState;
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typedef struct VesaPsrConfig
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{
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NvU8 psrCfgEnable : 1;
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NvU8 srcTxEnabledInPsrActive : 1;
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NvU8 crcVerifEnabledInPsrActive : 1;
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NvU8 frameCaptureSecondActiveFrame : 1;
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NvU8 selectiveUpdateOnSecondActiveline : 1;
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NvU8 enableHpdIrqOnCrcMismatch : 1;
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NvU8 enablePsr2 : 1;
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NvU8 reserved : 1;
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} vesaPsrConfig;
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typedef struct VesaPsrDebugStatus
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{
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NvBool lastSdpPsrState;
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NvBool lastSdpUpdateRfb;
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NvBool lastSdpCrcValid;
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NvBool lastSdpSuValid;
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NvBool lastSdpFirstSURcvd;
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NvBool lastSdpLastSURcvd;
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NvBool lastSdpYCoordValid;
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NvU8 maxResyncFrames;
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NvU8 actualResyncFrames;
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} vesaPsrDebugStatus;
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typedef struct VesaPsrErrorStatus
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{
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NvU8 linkCrcError : 1;
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NvU8 rfbStoreError : 1;
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NvU8 vscSdpError : 1;
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NvU8 rsvd : 5;
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} vesaPsrErrorStatus;
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typedef struct VesaPsrEventIndicator
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{
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NvU8 sinkCapChange : 1;
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NvU8 rsvd : 7;
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} vesaPsrEventIndicator;
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#pragma pack(1)
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typedef struct VesaPsrSinkCaps
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{
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NvU8 psrVersion;
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NvU8 linkTrainingRequired : 1;
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NvU8 psrSetupTime : 3;
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NvU8 yCoordinateRequired : 1;
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NvU8 psr2UpdateGranularityRequired : 1;
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NvU8 reserved : 2;
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NvU16 suXGranularity;
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NvU8 suYGranularity;
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} vesaPsrSinkCaps;
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#pragma pack()
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typedef struct PanelReplayCaps
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{
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NvBool panelReplaySupported;
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} panelReplayCaps;
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typedef struct PanelReplayConfig
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{
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NvBool enablePanelReplay;
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} panelReplayConfig;
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// PR state
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typedef enum
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{
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PanelReplay_Inactive = 0,
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PanelReplay_CaptureAndDisplay = 1,
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PanelReplay_DisplayFromRfb = 2,
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PanelReplay_Undefined = 7
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} PanelReplayState;
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typedef struct
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{
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PanelReplayState prState;
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} PanelReplayStatus;
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// Multiplier constant to get link frequency in KHZ
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// Maximum link rate of Main Link lanes = Value x 270M.
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// To get it to KHz unit, we need to multiply 270K.
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#define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000)
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// Multiplier constant to get link rate table's in KHZ
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#define DP_LINK_RATE_TABLE_MULTIPLIER_KHZ 200
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//
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// Multiplier constant to get link frequency (multiplier of 270MHz) in MBps
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// a * 270 * 1000 * 1000(270Mhz) * (8 / 10)(8b/10b) / 8(Byte)
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// = a * 27000000
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//
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#define DP_LINK_BW_FREQ_MULTI_MBPS 27000000
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//
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// Get link rate in multiplier of 270MHz from KHz:
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// a * 1000(KHz) / 270 * 1000 * 1000(270Mhz)
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//
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#define LINK_RATE_KHZ_TO_MULTP(a) ((a) / 270000)
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//
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// Get link rate in MBps from KHz:
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// a * 1000 * (8 / 10)(8b/10b) / 8(Byte)
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// = a * 100
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//
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#define LINK_RATE_KHZ_TO_MBPS(a) ((a) * 100)
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#define DP_MAX_LANES 8 // This defines the maximum number of lanes supported on a chip.
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#define DP_MAX_LANES_PER_LINK 4 // This defines the maximum number of lanes per link in a chip.
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#define DP_AUX_CHANNEL_MAX_BYTES 16
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#define DP_CLOCK_RECOVERY_TOT_TRIES 10
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#define DP_CLOCK_RECOVERY_MAX_TRIES 5
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#define DP_CH_EQ_MAX_RETRIES 5
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#define DP_LT_MAX_FOR_MST_MAX_RETRIES 3
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#define DP_READ_EDID_MAX_RETRIES 7
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#define DP_AUX_CHANNEL_DEFAULT_DEFER_MAX_TRIES 7
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#define DP_AUX_CHANNEL_TIMEOUT_MAX_TRIES 2
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#define DP_SET_POWER_D0_NORMAL_MAX_TRIES 3
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#define DP_SW_AUTO_READ_REQ_SIZE 6
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#define NV_DP_RBR_FALLBACK_MAX_TRIES 3
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#define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_DEFAULT_MS 1
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#define DP_AUX_CHANNEL_TIMEOUT_WAITIDLE 400 // source is required to wait at least 400us before it considers the AUX transaction to have timed out.
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#define DP_AUX_CHANNEL_TIMEOUT_VALUE_DEFAULT 400
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#define DP_AUX_CHANNEL_TIMEOUT_VALUE_MAX 3200
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#define DP_PHY_REPEATER_INDEX_FOR_SINK 0xFFFFFFFF
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#define DP_MESSAGEBOX_SIZE 48
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#define DP_POST_LT_ADJ_REQ_LIMIT 6
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#define DP_POST_LT_ADJ_REQ_TIMER 200000
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#define DP_AUX_HYBRID_TIMEOUT 600
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#define DP_AUX_SEMA_ACQUIRE_TIMEOUT 20000
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#define DP_CONFIG_WATERMARK_ADJUST 2
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#define DP_CONFIG_WATERMARK_LIMIT 20
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#define DP_CONFIG_INCREASED_WATERMARK_ADJUST 8
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#define DP_CONFIG_INCREASED_WATERMARK_LIMIT 22
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#define NV_DP_MSA_PROPERTIES_MISC1_STEREO 2:1
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#define DP_LANE_STATUS_ARRAY_SIZE ((displayPort_LaneSupported + 1) / 2)
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#define DP_LANE_STATUS_ARRAY_INDEX(lane) ((lane) < displayPort_LaneSupported ? ((lane) / 2) : 0)
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#define IS_VALID_LANECOUNT(val) (((NvU32)(val)==0) || ((NvU32)(val)==1) || \
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((NvU32)(val)==2) || ((NvU32)(val)==4) || \
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((NvU32)(val)==8))
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#define IS_STANDARD_LINKBW(val) (((NvU32)(val)==linkBW_1_62Gbps) || \
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((NvU32)(val)==linkBW_2_70Gbps) || \
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((NvU32)(val)==linkBW_5_40Gbps) || \
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((NvU32)(val)==linkBW_8_10Gbps))
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#define IS_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \
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((NvU32)(val)==linkBW_2_43Gbps) || \
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((NvU32)(val)==linkBW_3_24Gbps) || \
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((NvU32)(val)==linkBW_4_32Gbps))
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#define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \
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IS_INTERMEDIATE_LINKBW(val))
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//
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// Phy Repeater count read from DPCD offset F0002h is an
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// 8 bit value where each bit represents the total count
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// 80h = 1 repeater, 40h = 2 , 20h = 3 ... 01h = 8
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// This function maps it to decimal system
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//
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static NV_INLINE NvU32 mapPhyRepeaterVal(NvU32 value)
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{
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switch (value)
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{
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case NV_DPCD14_PHY_REPEATER_CNT_VAL_0:
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return 0;
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case NV_DPCD14_PHY_REPEATER_CNT_VAL_1:
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return 1;
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case NV_DPCD14_PHY_REPEATER_CNT_VAL_2:
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return 2;
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case NV_DPCD14_PHY_REPEATER_CNT_VAL_3:
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return 3;
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case NV_DPCD14_PHY_REPEATER_CNT_VAL_4:
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return 4;
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case NV_DPCD14_PHY_REPEATER_CNT_VAL_5:
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return 5;
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case NV_DPCD14_PHY_REPEATER_CNT_VAL_6:
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return 6;
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case NV_DPCD14_PHY_REPEATER_CNT_VAL_7:
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return 7;
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case NV_DPCD14_PHY_REPEATER_CNT_VAL_8:
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return 8;
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default:
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return 0;
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}
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}
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// HDCP specific definitions
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#define HDCP22_RTX_SIMPLE_PATTERN 0x12345678
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#define HDCP22_TX_CAPS_PATTERN_BIG_ENDIAN {0x02, 0x00, 0x00}
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#define DP_MST_HEAD_TO_STREAMID(head, pipeId, numHeads) ((head) + 1 + (pipeId) * (numHeads))
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#define DP_MST_STREAMID_TO_HEAD(streamid, pipeId, numHeads) ((streamid) - 1 - ((pipeId) * (numHeads)))
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#define DP_MST_STREAMID_TO_PIPE(streamid, head, numHeads) (((streamid) - (head) - 1) / (numHeads))
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|
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typedef enum
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|
{
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NV_DP_SBMSG_REQUEST_ID_GET_MESSAGE_TRANSACTION_VERSION = 0x00,
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NV_DP_SBMSG_REQUEST_ID_LINK_ADDRESS = 0x01,
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NV_DP_SBMSG_REQUEST_ID_CONNECTION_STATUS_NOTIFY = 0x02,
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NV_DP_SBMSG_REQUEST_ID_ENUM_PATH_RESOURCES = 0x10,
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NV_DP_SBMSG_REQUEST_ID_ALLOCATE_PAYLOAD = 0x11,
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NV_DP_SBMSG_REQUEST_ID_QUERY_PAYLOAD = 0x12,
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NV_DP_SBMSG_REQUEST_ID_RESOURCE_STATUS_NOTIFY = 0x13,
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NV_DP_SBMSG_REQUEST_ID_CLEAR_PAYLOAD_ID_TABLE = 0x14,
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|
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NV_DP_SBMSG_REQUEST_ID_REMOTE_DPCD_READ = 0x20,
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NV_DP_SBMSG_REQUEST_ID_REMOTE_DPCD_WRITE = 0x21,
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NV_DP_SBMSG_REQUEST_ID_REMOTE_I2C_READ = 0x22,
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NV_DP_SBMSG_REQUEST_ID_REMOTE_I2C_WRITE = 0x23,
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NV_DP_SBMSG_REQUEST_ID_POWER_UP_PHY = 0x24,
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|
NV_DP_SBMSG_REQUEST_ID_POWER_DOWN_PHY = 0x25,
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|
|
|
NV_DP_SBMSG_REQUEST_ID_SINK_EVENT_NOTIFY = 0x30,
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|
NV_DP_SBMSG_REQUEST_ID_QUERY_STREAM_ENCRYPTION_STATUS = 0x38,
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|
|
|
NV_DP_SBMSG_REQUEST_ID_UNDEFINED = 0xFF,
|
|
} NV_DP_SBMSG_REQUEST_ID;
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|
|
|
// FEC
|
|
|
|
#define NV_DP_FEC_FLAGS_SELECT_ALL 0x7
|
|
#define NV_DP_ERROR_COUNTERS_PER_LANE 5
|
|
#define NV_DP_MAX_NUM_OF_LANES 4
|
|
#define NV_DP_FEC_ERROR_COUNT_INVALID 0xbadf
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|
#define NV_DP_UNCORRECTED_ERROR NV_DP_FEC_UNCORRECTED : NV_DP_FEC_UNCORRECTED
|
|
#define NV_DP_CORRECTED_ERROR NV_DP_FEC_CORRECTED : NV_DP_FEC_CORRECTED
|
|
#define NV_DP_BIT_ERROR NV_DP_FEC_BIT : NV_DP_FEC_BIT
|
|
#define NV_DP_PARITY_BLOCK_ERROR NV_DP_FEC_PARITY_BLOCK : NV_DP_FEC_PARITY_BLOCK
|
|
#define NV_DP_PARITY_BIT_ERROR NV_DP_FEC_PARITY_BIT : NV_DP_FEC_PARITY_BIT
|
|
#define NV_DP_UNCORRECTED_ERROR_NO 0
|
|
#define NV_DP_UNCORRECTED_ERROR_YES 1
|
|
#define NV_DP_CORRECTED_ERROR_NO 0
|
|
#define NV_DP_CORRECTED_ERROR_YES 1
|
|
#define NV_DP_BIT_ERROR_NO 0
|
|
#define NV_DP_BIT_ERROR_YES 1
|
|
#define NV_DP_PARITY_BLOCK_ERROR_NO 0
|
|
#define NV_DP_PARITY_BLOCK_ERROR_YES 1
|
|
#define NV_DP_PARITY_BIT_ERROR_NO 0
|
|
#define NV_DP_PARITY_BIT_ERROR_YES 1
|
|
|
|
|
|
#endif // #ifndef _DISPLAYPORT_H_
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