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448 lines
19 KiB
C
448 lines
19 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrl0041.finn
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//
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#include "nvos.h"
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#include "ctrl/ctrlxxxx.h"
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/* NV04_MEMORY control commands and parameters */
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#define NV0041_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0041, NV0041_CTRL_##cat, idx)
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/* NV04_MEMORY command categories (6bits) */
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#define NV0041_CTRL_RESERVED (0x00)
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#define NV0041_CTRL_MEMORY (0x01)
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/*
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* NV0041_CTRL_CMD_NULL
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*
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* This command does nothing.
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* This command does not take any parameters.
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*
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* Possible status values returned are:
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* NV_OK
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*/
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#define NV0041_CTRL_CMD_NULL (0x410000) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID << 8) | 0x0" */
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/*
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* NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR
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*
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* This command returns attributes associated with the memory object
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* at the given offset. The architecture dependent return parameter
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* comprFormat determines the meaningfulness (or not) of comprOffset.
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*
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* This call is only currently supported in the MODS environment.
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*
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* memOffset
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* This parameter is both an input and an output. As input, this
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* parameter holds an offset into the memory surface. The return
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* value is the physical address of the surface at the given offset.
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* memFormat
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* This parameter returns the memory kind of the surface.
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* comprOffset
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* This parameter returns the compression offset of the surface.
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* comprFormat
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* This parameter returns the type of compression of the surface.
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* memAperture
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* The aperture of the surface is returned in this field.
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* Legal return values for this parameter are
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* NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM
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* NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM
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* gpuCacheAttr
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* gpuCacheAttr returns the gpu cache attribute of the surface.
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* Legal return values for this field are
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* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
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* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
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* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
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* gpuP2PCacheAttr
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* gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface.
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* Legal return values for this field are
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* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
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* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
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* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
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* mmuContext
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* mmuContext indicates the type of physical address to be returned (input parameter).
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* Legal return values for this field are
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* TEGRA_VASPACE_A -- return the device physical address for Tegra (non-GPU) engines. This is the system physical address itself.
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* returns the system physical address. This may change to use a class value in future.
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* FERMI_VASPACE_A -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address.
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* 0 -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address.
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* use of zero may be deprecated in future.
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* contigSegmentSize
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* If the underlying surface is physically contiguous, this parameter
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* returns the size in bytes of the piece of memory starting from
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* the offset specified in the memOffset parameter extending to the last
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* byte of the surface.
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*
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* Possible status values returned are:
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* NV_OK
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* NVOS_STATUS_BAD_OBJECT_HANDLE
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* NVOS_STATUS_BAD_OBJECT_PARENT
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* NVOS_STATUS_NOT_SUPPORTED
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*
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*/
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#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x410103) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x3U)
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typedef struct NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS {
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NV_DECLARE_ALIGNED(NvU64 memOffset, 8);
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NvU32 memFormat;
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NvU32 comprOffset;
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NvU32 comprFormat;
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NvU32 memAperture;
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NvU32 gpuCacheAttr;
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NvU32 gpuP2PCacheAttr;
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NvU32 mmuContext;
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NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8);
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} NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS;
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/* valid memAperture return values */
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#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM (0x00000000)
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#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM (0x00000001)
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/* valid gpuCacheAttr return values */
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#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000)
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#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED (0x00000001)
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#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED (0x00000002)
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/*
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* NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID
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*
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* This command returns the Z-cull identifier for a surface.
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* The value of ~0 is returned if there is none associated.
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*
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* Possible status values returned are:
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* NV_OK
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* NVOS_STATUS_BAD_OBJECT_HANDLE
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* NVOS_STATUS_BAD_OBJECT_PARENT
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* NVOS_STATUS_NOT_SUPPORTED
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*
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*/
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#define NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID (0x410104) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID (0x4U)
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typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS {
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NvU32 zcullId;
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} NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS;
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// return values for 'tilingFormat'
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// XXX - the names for these are misleading
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#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_INVALID (0x00000000)
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#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB (0x00000001)
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#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_1HIGH (0x00000002)
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#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_4HIGH (0x00000003)
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#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_1HIGH (0x00000004)
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#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_4HIGH (0x00000005)
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/*
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* NV0041_CTRL_SURFACE_INFO
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*
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* This structure represents a single 32bit surface value. Clients
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* request a particular surface value by specifying a unique surface
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* information index.
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*
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* Legal surface information index values are:
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* NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS
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* This index is used to request the set of hw attributes associated
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* with the surface. Each distinct attribute is represented by a
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* single bit flag in the returned value.
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* Legal flags values for this index are:
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* NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR
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* This surface has compression resources bound to it.
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* NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL
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* This surface has zcull resources bound to it.
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* NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE
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* This index is used to request the compression coverage (if any)
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* in units of 64K for the associated surface. A value of zero indicates
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* there are no compression resources associated with the surface.
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* Legal return values range from zero to a maximum number of 64K units
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* that is GPU implementation dependent.
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* NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE
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* This index is used to request the physically allocated size in units
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* of 4K(NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR) for the associated
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* surface.
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* NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR
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* This index is used to request the surface attribute field. The returned
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* field value can be decoded using the NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_*
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* DRF-style macros provided below.
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* NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE
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* This index is used to request the surface address space type.
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* Returned values are described by NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE.
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*/
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typedef NVXXXX_CTRL_XXX_INFO NV0041_CTRL_SURFACE_INFO;
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/* valid surface info index values */
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#define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS (0x00000001)
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#define NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE (0x00000005)
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#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE (0x00000007)
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#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR (0x00000008)
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#define NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE (0x00000009)
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/*
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* This define indicates the scale factor of the reported physical size to the
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* actual size in bytes. We use the scale factor to save space from the
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* interface and account for large surfaces. To get the actual size,
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* use `(NvU64)reported_size * NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR`.
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*/
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#define NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR (0x1000)
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/* valid surface info attr flags */
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#define NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR (0x00000002)
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#define NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL (0x00000004)
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/* Valid surface info page size */
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE NVOS32_ATTR_PAGE_SIZE
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_DEFAULT NVOS32_ATTR_PAGE_SIZE_DEFAULT
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_4KB NVOS32_ATTR_PAGE_SIZE_4KB
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_BIG NVOS32_ATTR_PAGE_SIZE_BIG
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_HUGE NVOS32_ATTR_PAGE_SIZE_HUGE
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/* Valid surface info CPU coherency */
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY NVOS32_ATTR_COHERENCY
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_UNCACHED NVOS32_ATTR_COHERENCY_UNCACHED
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_CACHED NVOS32_ATTR_COHERENCY_CACHED
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_COMBINE NVOS32_ATTR_COHERENCY_WRITE_COMBINE
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_THROUGH NVOS32_ATTR_COHERENCY_WRITE_THROUGH
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_PROTECT NVOS32_ATTR_COHERENCY_WRITE_PROTECT
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#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_BACK NVOS32_ATTR_COHERENCY_WRITE_BACK
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/*
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* NV0041_CTRL_CMD_GET_SURFACE_INFO
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*
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* This command returns surface information for the associated memory object.
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* Requests to retrieve surface information use a list of one or more
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* NV0041_CTRL_SURFACE_INFO structures.
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*
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* surfaceInfoListSize
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* This field specifies the number of entries on the caller's
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* surfaceInfoList.
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* surfaceInfoList
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* This field specifies a pointer in the caller's address space
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* to the buffer into which the surface information is to be returned.
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* This buffer must be at least as big as surfaceInfoListSize multiplied
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* by the size of the NV0041_CTRL_SURFACE_INFO structure.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_OPERATING_SYSTEM
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*/
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#define NV0041_CTRL_CMD_GET_SURFACE_INFO (0x410110) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID (0x10U)
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typedef struct NV0041_CTRL_GET_SURFACE_INFO_PARAMS {
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NvU32 surfaceInfoListSize;
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NV_DECLARE_ALIGNED(NvP64 surfaceInfoList, 8);
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} NV0041_CTRL_GET_SURFACE_INFO_PARAMS;
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/*
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* NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE
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*
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* This command returns the percentage of surface compression tag coverage.
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* The value of 0 is returned if there are no tags associated.
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*
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* Possible status values returned are:
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* NV_OK
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* NVOS_STATUS_BAD_OBJECT_HANDLE
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* NVOS_STATUS_BAD_OBJECT_PARENT
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* NVOS_STATUS_NOT_SUPPORTED
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*
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*/
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#define NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE (0x410112) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID (0x12U)
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typedef struct NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS {
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NvHandle hSubDevice; /* if non zero subDevice handle of local GPU */
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NvU32 lineMin;
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NvU32 lineMax;
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NvU32 format;
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} NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS;
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/*
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* NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR
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*
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* This command returns the BAR1 physical address of a
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* Memory mapping made using NvRmMapMemory()
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*
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* Possible status values returned are:
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* NV_OK
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* NVOS_STATUS_INVALID_DATA
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* NV_ERR_INVALID_CLIENT
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* NV_ERR_INVALID_OBJECT_HANDLE
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*
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*/
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#define NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR (0x410114) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID (0x14U)
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typedef struct NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS {
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NV_DECLARE_ALIGNED(NvP64 pLinearAddress, 8); /* [in] Linear address of CPU mapping */
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NV_DECLARE_ALIGNED(NvU64 busAddress, 8); /* [out] BAR1 address */
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} NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS;
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/*
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* NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
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*
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* This command flushes a cache on the GPU which all memory accesses go
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* through. The types of flushes supported by this API may not be supported by
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* all hardware. Attempting an unsupported flush type will result in an error.
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*
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* flags
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* Contains flags to control various aspects of the flush. Valid values
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* are defined in NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS*. Not all
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* flags are valid for all GPUs.
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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* NVOS_STATUS_INVALID_ARGUMENT
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* NVOS_STATUS_INVALID_STATE
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*
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* See Also:
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* NV0080_CTRL_CMD_DMA_FLUSH
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* Performs flush operations in broadcast for the GPU cache and other hardware
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* engines. Use this call if you want to flush all GPU caches in a
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* broadcast device.
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* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
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* Flushes the entire GPU cache or a set of physical addresses (if the
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* hardware supports it). Use this call if you want to flush a set of
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* addresses or the entire GPU cache in unicast mode.
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*
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*/
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#define NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE (0x410116) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0x16U)
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typedef struct NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS {
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NvU32 flags;
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} NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS;
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#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK 0:0
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#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000)
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#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001)
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#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE 1:1
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#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000)
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#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001)
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/*
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* NV0041_CTRL_CMD_GET_EME_PAGE_SIZE
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*
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* This command may be used to get the memory page size
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*
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* Parameters:
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* pageSize [OUT]
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* pageSize with associated memory descriptor
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*
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* Possible status values are:
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* NV_OK
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* NV_ERR_INVALID_OBJECT_HANDLE
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* NV_ERR_NOT_SUPPORTED
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*/
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#define NV0041_CTRL_CMD_GET_MEM_PAGE_SIZE (0x410118) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U)
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typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS {
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NV_DECLARE_ALIGNED(NvU64 pageSize, 8); /* [out] - page size */
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} NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS;
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/*
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* NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION
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*
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* Acquire/release compression for surface
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*
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* Parameters:
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* bRelease [IN]
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* true = release compression; false = acquire compression
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*/
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#define NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION (0x410119) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID (0x19U)
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typedef struct NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS {
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NvBool bRelease; /* [in] - acquire/release setting */
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} NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS;
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#define NV0041_CTRL_CMD_PRINT_LABELS_PARAMS_MESSAGE_ID (0x50U)
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typedef struct NV0041_CTRL_CMD_PRINT_LABELS_PARAMS {
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NvU32 tag; /* [in] */
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} NV0041_CTRL_CMD_PRINT_LABELS_PARAMS;
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#define NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID (0x51U)
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typedef struct NV0041_CTRL_CMD_SET_LABEL_PARAMS {
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NvU32 tag; /* [in] */
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} NV0041_CTRL_CMD_SET_LABEL_PARAMS;
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#define NV0041_CTRL_CMD_SET_LABEL (0x410151) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_CMD_GET_LABEL (0x410152) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID (0x52U)
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typedef struct NV0041_CTRL_CMD_GET_LABEL_PARAMS {
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NvU32 tag; /* [in] */
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} NV0041_CTRL_CMD_GET_LABEL_PARAMS;
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|
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/*
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* NV0041_CTRL_CMD_SET_TAG
|
|
*
|
|
* This command sets memory allocation tag used for debugging.
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* Every client has it's own memory allocation tag and tag is copying when object is duping.
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* This control can be used for shared allocations to change it's tag.
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*/
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#define NV0041_CTRL_CMD_SET_TAG (0x410120) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID (0x20U)
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typedef struct NV0041_CTRL_CMD_SET_TAG_PARAMS {
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|
NvU32 tag; /* [in] */
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|
} NV0041_CTRL_CMD_SET_TAG_PARAMS;
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|
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/*
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|
* NV0041_CTRL_CMD_GET_TAG
|
|
*
|
|
* This command returns memory allocation tag used for debugging.
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|
*/
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#define NV0041_CTRL_CMD_GET_TAG (0x410121) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID" */
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#define NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID (0x21U)
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typedef struct NV0041_CTRL_CMD_GET_TAG_PARAMS {
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|
NvU32 tag; /* [out] */
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|
} NV0041_CTRL_CMD_GET_TAG_PARAMS;
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|
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/* _ctrl0041_h_ */
|