mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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138 lines
11 KiB
C
138 lines
11 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __gh100_clc8b5_h__
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#define __gh100_clc8b5_h__
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#define HOPPER_DMA_COPY_A (0x0000C8B5)
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#define NVC8B5_SET_SEMAPHORE_A (0x00000240)
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#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0
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#define NVC8B5_SET_SEMAPHORE_B (0x00000244)
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#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0
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#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248)
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#define NVC8B5_SET_SRC_PHYS_MODE (0x00000260)
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#define NVC8B5_SET_SRC_PHYS_MODE_TARGET 1:0
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#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
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#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
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#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
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#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003)
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#define NVC8B5_SET_SRC_PHYS_MODE_PEER_ID 8:6
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#define NVC8B5_SET_SRC_PHYS_MODE_FLA 9:9
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#define NVC8B5_SET_DST_PHYS_MODE (0x00000264)
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#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0
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#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
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#define NVC8B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
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#define NVC8B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
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#define NVC8B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003)
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#define NVC8B5_LAUNCH_DMA (0x00000300)
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#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
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#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000)
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#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001)
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#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002)
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#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2
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#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000)
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#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001)
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#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE 25:25
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#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000)
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#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001)
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001)
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002)
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001)
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#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7
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#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001)
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#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8
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#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001)
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#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9
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#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000)
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#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10
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#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000)
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#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001)
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#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12
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#define NVC8B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000)
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#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
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#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13
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#define NVC8B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000)
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#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006)
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001)
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001)
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#define NVC8B5_LAUNCH_DMA_COPY_TYPE 21:20
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#define NVC8B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000)
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#define NVC8B5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000)
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#define NVC8B5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001)
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#define NVC8B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT (0x00000002)
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#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23
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#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE (0x00000000)
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#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001)
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#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26
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#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001)
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27
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#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000)
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#define NVC8B5_OFFSET_IN_UPPER (0x00000400)
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#define NVC8B5_OFFSET_IN_UPPER_UPPER 24:0
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#define NVC8B5_OFFSET_IN_LOWER (0x00000404)
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#define NVC8B5_OFFSET_IN_LOWER_VALUE 31:0
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#define NVC8B5_OFFSET_OUT_UPPER (0x00000408)
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#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0
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#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C)
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#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0
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#define NVC8B5_LINE_LENGTH_IN (0x00000418)
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#define NVC8B5_SET_SECURE_COPY_MODE (0x00000500)
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#define NVC8B5_SET_SECURE_COPY_MODE_MODE 0:0
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#define NVC8B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT (0x00000000)
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#define NVC8B5_SET_SECURE_COPY_MODE_MODE_DECRYPT (0x00000001)
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#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER (0x00000514)
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#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER 24:0
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#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER (0x00000518)
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#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER 31:0
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#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER (0x00000530)
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#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER 24:0
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#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER (0x00000534)
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#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER 31:0
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#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER (0x00000538)
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#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER 24:0
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#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER (0x0000053C)
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#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER 31:0
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#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC)
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#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0
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#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000)
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#define NVC8B5_SET_REMAP_CONST_A (0x00000700)
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#define NVC8B5_SET_REMAP_CONST_B (0x00000704)
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#define NVC8B5_SET_REMAP_COMPONENTS (0x00000708)
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#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0
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#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004)
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#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005)
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#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y 6:4
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#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005)
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#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16
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#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000)
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#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003)
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#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24
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#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000)
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#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001)
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#endif // __gh100_clc8b5_h__
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