ROCm/composable_kernel
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Merge commit 'd7278cc664c20613e0b7c45f249f6e7613550ca2' into develop

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assistant-librarian[bot]
2025-10-16 16:13:55 +00:00
parent 75be611080
commit 1b7c5502e2
8 changed files with 1482 additions and 4 deletions
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example/ck_tile/01_fmha/codegen/ops/fmha_fwd.py
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@@ -608,7 +608,7 @@ class KernelComponentFactory:
else:
pipelines.append(FmhaFwdPipeline('qr_async', 'row', 't', 'f', 't', 't', logits, bias, lse, dropout, squant, mask, skip, 'f'))
pipelines.append(FmhaFwdPipeline('qr_async', 'row', 't', 't', 't', 't', logits, bias, lse, dropout, squant, mask, skip, 'f'))
if (hdim, hdim_v) in [(64, 64), (128, 128)] and logits == "f" and bias == "no" and dropout == "f" and skip == "f":
if (hdim, hdim_v) in [(64, 64), (128, 128)] and logits == "f" and bias == "no" and dropout == "f" and lse == "f" and skip == "f":
pipelines.append(FmhaFwdPipeline('qr_async_trload', 'row', 'f', 'f', 'f', 'f', logits, bias, lse, dropout, squant, mask, skip, 't'))
pipelines.append(FmhaFwdPipeline('qr_async_trload', 'row', 'f', 'f', 't', 't', logits, bias, lse, dropout, squant, mask, skip, 't'))
if receipt == 1 and bias != "bias":