mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-04 13:41:24 +00:00
adaptive scheduler instead of Macro definition
This commit is contained in:
valarLip
@@ -118,6 +118,9 @@ struct FlatmmPipelineAGmemBGmemCRegV1 : public BaseFlatmmPipelineAGmemBGmemCRegV
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static constexpr bool HasHotLoop = Problem::HasHotLoop;
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static constexpr auto TailNum = Problem::TailNum;
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static constexpr auto warp_m = WarpTile::at(idxM);
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static constexpr auto warp_n = WarpTile::at(idxN);
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static constexpr auto warp_k = WarpTile::at(idxK);
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/*
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defined(USING_MFMA_16x16x32) && defined(ENABLE_FP8) // mi300 fp8 16c 0.5*K1
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defined(USING_MFMA_32x32x16) && defined(ENABLE_FP8) // mi300 fp8 32c 0.5*K1
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@@ -132,24 +135,74 @@ struct FlatmmPipelineAGmemBGmemCRegV1 : public BaseFlatmmPipelineAGmemBGmemCRegV
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defined(USING_MFMA_16x16x128) && defined(ENABLE_FP4) // mi350 fp4 16c 1*K1
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defined(USING_MFMA_32x32x64) && defined(ENABLE_FP4) // mi350 fp4 32c 1*K1
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*/
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struct MfmaConfig
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{
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int mfma_per_wg;
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int dsread_per_wg;
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};
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static constexpr MfmaConfig GetMfmaConfig()
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{
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#if (defined(USING_MFMA_16x16x32_F8) || \
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defined(USING_MFMA_32x32x16_F8) || \
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defined(USING_MFMA_16x16x16_F16) || \
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defined(USING_MFMA_32x32x8_F16)) // K1 per Mfma = 0.5
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static constexpr auto mfma_per_wg = 2;
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static constexpr auto dsread_per_wg = 1;
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#elif (defined(USING_MFMA_16x16x32_F16) || \
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defined(USING_MFMA_32x32x16_F16) || \
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defined(USING_MFMA_16x16x128_F4) || \
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defined(USING_MFMA_32x32x64_F4)) // K1 per Mfma = 1
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static constexpr auto mfma_per_wg = 1;
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static constexpr auto dsread_per_wg = 1;
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#elif (defined(USING_MFMA_16x16x128_F8) || \
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defined(USING_MFMA_32x32x64_F8)) // K1 per Mfma = 2
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static constexpr auto mfma_per_wg = 1;
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static constexpr auto dsread_per_wg = 2;
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#endif
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// K1 per Mfma = 0.5 cases: mfma_per_wg = 2, dsread_per_wg = 1
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if constexpr((warp_m == 16 && warp_n == 16 && warp_k == 32 &&
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std::is_same_v<ADataType, fp8_t>) ||
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(warp_m == 32 && warp_n == 32 && warp_k == 16 &&
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std::is_same_v<ADataType, fp8_t>) ||
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(warp_m == 16 && warp_n == 16 && warp_k == 16 &&
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std::is_same_v<ADataType, fp16_t>) ||
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(warp_m == 32 && warp_n == 32 && warp_k == 8 &&
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std::is_same_v<ADataType, fp16_t>))
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{
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return {2, 1};
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}
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// K1 per Mfma = 2 cases: mfma_per_wg = 1, dsread_per_wg = 2
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else if constexpr((warp_m == 16 && warp_n == 16 && warp_k == 128 &&
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std::is_same_v<ADataType, fp8_t>) ||
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(warp_m == 32 && warp_n == 32 && warp_k == 64 &&
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std::is_same_v<ADataType, fp8_t>))
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{
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return {1, 2};
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}
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// K1 per Mfma = 1 cases: mfma_per_wg = 1, dsread_per_wg = 1
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else if constexpr((warp_m == 16 && warp_n == 16 && warp_k == 32 &&
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std::is_same_v<ADataType, fp16_t>) ||
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(warp_m == 32 && warp_n == 32 && warp_k == 16 &&
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std::is_same_v<ADataType, fp16_t>) ||
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(warp_m == 16 && warp_n == 16 && warp_k == 128 /*&&
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std::is_same_v<ADataType, fp4_t> */) ||
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(warp_m == 32 && warp_n == 32 && warp_k == 64 /*&&
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std::is_same_v<ADataType, fp4_t> */))
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{
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return {1, 1};
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}
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// Default configuration
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else
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{
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return {1, 1};
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}
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}
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static constexpr auto mfma_config = GetMfmaConfig();
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static constexpr auto mfma_per_wg = mfma_config.mfma_per_wg;
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static constexpr auto dsread_per_wg = mfma_config.dsread_per_wg;
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// #if (defined(USING_MFMA_16x16x32_F8) || \
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// defined(USING_MFMA_32x32x16_F8) || \
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// defined(USING_MFMA_16x16x16_F16) || \
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// defined(USING_MFMA_32x32x8_F16)) // K1 per Mfma = 0.5
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// static constexpr auto mfma_per_wg = 2;
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// static constexpr auto dsread_per_wg = 1;
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// #elif (defined(USING_MFMA_16x16x32_F16) || \
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// defined(USING_MFMA_32x32x16_F16) || \
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// defined(USING_MFMA_16x16x128_F4) || \
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// defined(USING_MFMA_32x32x64_F4)) // K1 per Mfma = 1
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// static constexpr auto mfma_per_wg = 1;
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// static constexpr auto dsread_per_wg = 1;
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// #elif (defined(USING_MFMA_16x16x128_F8) || \
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// defined(USING_MFMA_32x32x64_F8)) // K1 per Mfma = 2
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// static constexpr auto mfma_per_wg = 1;
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// static constexpr auto dsread_per_wg = 2;
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// #endif
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[[nodiscard]] CK_TILE_HOST static const std::string GetName()
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{
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@@ -242,252 +295,260 @@ struct FlatmmPipelineAGmemBGmemCRegV1 : public BaseFlatmmPipelineAGmemBGmemCRegV
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// 0 M7N1: 62 - - - -
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// 0 M7N2: 63 - - 8 -
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// 0 M7N3: 64 4 - - -
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#if 0 // MI350 FP8 16X16 128*256*256
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static_for<0, 2, 1>{}([&](auto j) {
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ignore = j;
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static_for<0, 3, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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static_for<0, 3, 1>{}([&](auto i) {
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ignore = i;
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if constexpr(warp_m == 16 && warp_n == 16)
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{
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#if defined(__gfx950__) // MI350 FP8 16X16 128*256*256
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if constexpr(kMPerBlock == 128 && kNPerBlock == 256 && kKPerBlock == 256)
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{
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static_for<0, 2, 1>{}([&](auto j) {
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ignore = j;
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static_for<0, 3, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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static_for<0, 3, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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__builtin_amdgcn_sched_barrier(0);
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}
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else
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{
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static_for<0, 2, 1>{}([&](auto j) {
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ignore = j;
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static_for<0, 3, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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static_for<0, 3, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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});
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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__builtin_amdgcn_sched_barrier(0);
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}
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#else
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if constexpr(kMPerBlock == 128 && kNPerBlock == 128 && kKPerBlock == 128)
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{
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static_for<0, 2, 1>{}([&](auto j) {
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ignore = j;
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static_for<0, 2, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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static_for<0, 2, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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static_for<0, 1, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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static_for<0, 1, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
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__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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static_for<0, 1, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
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static_for<0, 1, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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});
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});
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__builtin_amdgcn_sched_barrier(0);
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}
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else if(kMPerBlock == 128 && kNPerBlock == 256 && kKPerBlock == 128)
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{
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static_for<0, 2, 1>{}([&](auto j) {
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ignore = j;
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static_for<0, 4, 1>{}([&](auto i) {
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ignore = i;
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
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||||
});
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||||
static_for<0, 1, 1>{}([&](auto i) {
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||||
ignore = i;
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||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
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||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
});
|
||||
__builtin_amdgcn_sched_barrier(0);
|
||||
}
|
||||
else if(kMPerBlock == 16 && kNPerBlock == 64 && kKPerBlock == 256)
|
||||
{
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
|
||||
__builtin_amdgcn_sched_barrier(0);
|
||||
#endif
|
||||
#if 0 // MI350 FP8 16X16
|
||||
static_for<0, 2, 1>{}([&](auto j) {
|
||||
ignore = j;
|
||||
static_for<0, 3, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
|
||||
static_for<0, 3, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
});
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
|
||||
__builtin_amdgcn_sched_barrier(0);
|
||||
#endif
|
||||
#if 0 // MI300 FP8 16X16 128*128*128
|
||||
static_for<0, 2, 1>{}([&](auto j) {
|
||||
ignore = j;
|
||||
static_for<0, 2, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 2, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
});
|
||||
|
||||
__builtin_amdgcn_sched_barrier(0);
|
||||
#endif
|
||||
#if 0 // MI300 FP8 16X16 128*256*128
|
||||
static_for<0, 2, 1>{}([&](auto j) {
|
||||
ignore = j;
|
||||
static_for<0, 4, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
});
|
||||
|
||||
__builtin_amdgcn_sched_barrier(0);
|
||||
#endif
|
||||
#if 0 //MI300 FP8 16X16 16*64*256
|
||||
static_for<0, 1, 1>{}([&](auto i) {
|
||||
ignore = i;
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
});
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x200, 1, 0); // DS write
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_group_barrier(0x008, 1, 0); // MFMA
|
||||
__builtin_amdgcn_sched_group_barrier(0x100, 1, 0); // DS read
|
||||
|
||||
__builtin_amdgcn_sched_group_barrier(0x020, 1, 0); // VMEM read
|
||||
__builtin_amdgcn_sched_barrier(0);
|
||||
#endif
|
||||
__builtin_amdgcn_sched_barrier(0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
CK_TILE_HOST_DEVICE static constexpr auto TailHotLoopScheduler()
|
||||
{
|
||||
#if 0
|
||||
|
||||
Reference in New Issue
Block a user