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https://github.com/ROCm/composable_kernel.git
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Standalone layernorm (#315)
* Implement layernorm kernel and deviceOp * verify gpu kernel with host code * 1. Separate gamma aand beta from affine 2. Check if argument is valid * clean * Sync the naming * Support sweep once mode if we can put k dimension data inside one block * [What] Get length from upper length. [Why] if we get length directly, we may get length after padding. * We only use one block in K dimension. Hence, we can simplify the indexing of global R/W. * Use 1d descriptor for gamma and beta * Add accElementwiseOp * Extract layernorm host code * Support different YVectorDim in GridwiseLayernorm * Rename XSrcVectorDim to XYSrcVectorDim. Because we use same parameter in deviceOp * Gamma and beta can share the VGPR. * Add test for fp32 and fp16 * Fix bug of concurrency and add test case which may fail orignally * Propagate NaN for layernorm Co-authored-by: Chao Liu <chao.liu2@amd.com>
This commit is contained in:
rocking5566
346
include/ck/tensor_operation/gpu/device/device_layernorm.hpp
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346
include/ck/tensor_operation/gpu/device/device_layernorm.hpp
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2022, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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#include <iostream>
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#include <sstream>
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#include "ck/utility/reduction_operator.hpp"
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#include "ck/tensor_operation/gpu/device/device_base.hpp"
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#include "ck/tensor_operation/gpu/device/device_reduce.hpp"
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#include "ck/tensor_operation/gpu/device/device_reduce_multiblock.hpp"
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#include "ck/tensor_operation/gpu/device/device_reduce_common.hpp"
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#include "ck/tensor_operation/gpu/grid/gridwise_layernorm.hpp"
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#include "ck/tensor_operation/gpu/grid/gridwise_set_buffer_value.hpp"
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#include "ck/device_utility/device_prop.hpp"
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#include "ck/device_utility/kernel_launch.hpp"
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namespace ck {
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namespace tensor_operation {
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namespace device {
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// Y = LayerNorm(X, Beta, Gamma)
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template <typename XDataType,
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typename GammaDataType,
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typename BetaDataType,
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typename AccDataType,
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typename YDataType,
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typename AccElementwiseOperation,
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index_t Rank,
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index_t NumReduceDim,
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index_t BlockSize,
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index_t MThreadClusterSize,
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index_t KThreadClusterSize,
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index_t MThreadSliceSize,
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index_t KThreadSliceSize,
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index_t XYSrcVectorDim,
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index_t XSrcVectorSize,
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index_t GammaSrcVectorSize,
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index_t BetaSrcVectorSize,
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index_t YDstVectorSize>
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struct DeviceLayernorm : public BaseOperator
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{
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static_assert(
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(KThreadSliceSize % GammaSrcVectorSize == 0),
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"Invalid thread slice sizes and/or gamma vector sizes configuration, please check!");
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static_assert(
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(KThreadSliceSize % BetaSrcVectorSize == 0),
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"Invalid thread slice sizes and/or beta vector sizes configuration, please check!");
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using PassThrough = tensor_operation::element_wise::PassThrough;
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// Used for freeloading of some handy functions from DeviceReduceMultiBlock
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using Reduction = DeviceReduceMultiBlock<XDataType,
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AccDataType,
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YDataType,
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Rank,
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NumReduceDim,
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reduce::Add,
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PassThrough, // InElementwiseOperation
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AccElementwiseOperation, // AccElementwiseOperation
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InMemoryDataOperationEnum::Set,
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false, // PropagateNan
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false, // OutputIndex
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false, // HaveIndexInputIfOutputIndex
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BlockSize,
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MThreadClusterSize,
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KThreadClusterSize,
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MThreadSliceSize,
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KThreadSliceSize,
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XYSrcVectorDim,
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XSrcVectorSize,
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1>; // YDstVectorSize
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static auto MakeAffine1dDescriptor(const std::vector<index_t>& Lengths,
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const std::vector<index_t>& Strides,
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int blkGroupSize,
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int numBlockTileIteration)
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{
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const auto tupleLengths = make_tuple_from_array(Lengths, Number<NumReduceDim>{});
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const auto tupleStrides = make_tuple_from_array(Strides, Number<NumReduceDim>{});
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auto desc = make_naive_tensor_descriptor(tupleLengths, tupleStrides);
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auto grid_desc_k = transform_tensor_descriptor(
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desc,
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make_tuple(make_merge_transform(tupleLengths)),
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make_tuple(typename arithmetic_sequence_gen<0, NumReduceDim, 1>::type{}),
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make_tuple(Sequence<0>{}));
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const auto reduceTotalLength = grid_desc_k.GetLength(Number<0>{});
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const int reduceSizePerBlock = Reduction::K_BlockTileSize * numBlockTileIteration;
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const auto Pad_K = reduceSizePerBlock * blkGroupSize - reduceTotalLength;
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auto grid_desc_k_padded = transform_tensor_descriptor(
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grid_desc_k,
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make_tuple(make_right_pad_transform(reduceTotalLength, Pad_K)),
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make_tuple(Sequence<0>{}),
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make_tuple(Sequence<0>{}));
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return (grid_desc_k_padded);
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};
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using GridDesc_M_K = decltype(Reduction::MakeSrc2dDescriptor({1}, {1}, 1, 1));
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using GridDesc_K = decltype(MakeAffine1dDescriptor({1}, {1}, 1, 1));
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using GridwiseReduceLayernormGeneric = GridwiseLayernorm_mk_to_mk<XDataType,
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GammaDataType,
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BetaDataType,
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YDataType,
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AccDataType,
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AccElementwiseOperation,
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GridDesc_M_K,
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GridDesc_K,
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BlockSize,
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MThreadClusterSize,
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KThreadClusterSize,
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MThreadSliceSize,
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KThreadSliceSize,
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XYSrcVectorDim,
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XSrcVectorSize,
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GammaSrcVectorSize,
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BetaSrcVectorSize,
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XYSrcVectorDim,
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YDstVectorSize,
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false>;
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using GridwiseReduceLayernormSweepOnce = GridwiseLayernorm_mk_to_mk<XDataType,
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GammaDataType,
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BetaDataType,
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YDataType,
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AccDataType,
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AccElementwiseOperation,
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GridDesc_M_K,
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GridDesc_K,
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BlockSize,
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MThreadClusterSize,
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KThreadClusterSize,
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MThreadSliceSize,
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KThreadSliceSize,
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XYSrcVectorDim,
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XSrcVectorSize,
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GammaSrcVectorSize,
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BetaSrcVectorSize,
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XYSrcVectorDim,
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YDstVectorSize,
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true>;
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struct Argument : public Reduction::Argument
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{
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Argument(const std::vector<index_t> lengths,
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const std::vector<index_t> xStrides,
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const std::vector<index_t> gammaStrides,
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const std::vector<index_t> betaStrides,
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const std::vector<index_t> reduceDims,
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AccElementwiseOperation acc_elementwise_op,
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AccDataType epsilon,
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const XDataType* p_x,
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const GammaDataType* p_gamma,
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const BetaDataType* p_beta,
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YDataType* p_y)
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: Reduction::Argument(lengths,
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xStrides,
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{},
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{},
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reduceDims,
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0.0f, // alpha
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0.0f, // beta
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p_x,
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nullptr,
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p_y,
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nullptr,
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acc_elementwise_op,
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PassThrough{}),
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epsilon_(epsilon),
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p_gamma_(p_gamma),
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p_beta_(p_beta),
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gammaStrides_(gammaStrides),
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betaStrides_(betaStrides)
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{
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reduceLength_.resize(NumReduceDim);
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for(int i = 0; i < NumReduceDim; ++i)
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{
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reduceLength_[i] = lengths[reduceDims[i]];
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}
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}
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AccDataType epsilon_;
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const GammaDataType* p_gamma_;
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const BetaDataType* p_beta_;
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std::vector<index_t> reduceLength_;
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std::vector<index_t> gammaStrides_;
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std::vector<index_t> betaStrides_;
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};
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struct Invoker : public BaseInvoker
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{
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float Run(const Argument& arg, const StreamConfig& stream_config = StreamConfig{})
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{
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const auto x_grid_desc_m_k = Reduction::MakeSrc2dDescriptor(
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arg.inLengths_, arg.inStrides_, arg.blkGroupSize, arg.numBlockTileIteration);
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const auto gamma_grid_desc_k = MakeAffine1dDescriptor(
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arg.reduceLength_, arg.gammaStrides_, arg.blkGroupSize, arg.numBlockTileIteration);
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const auto beta_grid_desc_k = MakeAffine1dDescriptor(
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arg.reduceLength_, arg.betaStrides_, arg.blkGroupSize, arg.numBlockTileIteration);
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const auto y_grid_desc_m_k = Reduction::MakeSrc2dDescriptor(
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arg.inLengths_, arg.inStrides_, arg.blkGroupSize, arg.numBlockTileIteration);
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bool sweep_once =
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x_grid_desc_m_k.GetLength(Number<1>{}) <= KThreadClusterSize * KThreadSliceSize;
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const auto kernel_main = sweep_once ? kernel_layernorm<GridwiseReduceLayernormSweepOnce,
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XDataType,
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GammaDataType,
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BetaDataType,
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YDataType,
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AccDataType,
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AccElementwiseOperation,
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GridDesc_M_K,
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GridDesc_K>
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: kernel_layernorm<GridwiseReduceLayernormGeneric,
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XDataType,
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GammaDataType,
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BetaDataType,
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YDataType,
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AccDataType,
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AccElementwiseOperation,
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GridDesc_M_K,
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GridDesc_K>;
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float avg_time = 0;
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avg_time += launch_and_time_kernel(stream_config,
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kernel_main,
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dim3(arg.gridSize),
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dim3(BlockSize),
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0,
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x_grid_desc_m_k,
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gamma_grid_desc_k,
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beta_grid_desc_k,
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y_grid_desc_m_k,
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arg.numBlockTileIteration,
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arg.epsilon_,
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arg.in_dev_,
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arg.p_gamma_,
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arg.p_beta_,
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arg.out_dev_,
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arg.acc_elementwise_op_);
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return (avg_time);
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};
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float Run(const BaseArgument* p_arg,
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const StreamConfig& stream_config = StreamConfig{}) override
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{
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return Run(*dynamic_cast<const Argument*>(p_arg), stream_config);
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};
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};
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bool IsSupportedArgument(const BaseArgument* p_arg) override
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{
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const Argument* p_arg_ = dynamic_cast<const Argument*>(p_arg);
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if(!Reduction::IsSupportedArgument(p_arg_))
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{
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return false;
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}
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if(p_arg_->inLengths_[Rank - 1] % YDstVectorSize != 0)
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{
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return false;
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}
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if(p_arg_->gammaStrides_.size() != NumReduceDim ||
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p_arg_->betaStrides_.size() != NumReduceDim)
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return false;
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auto IsScalarPerVectorValid = [](bool isLastDimensionCoalesced, int scalarPerVector) {
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bool ret = true;
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if(!isLastDimensionCoalesced)
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ret = scalarPerVector == 1;
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else
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ret = KThreadSliceSize % scalarPerVector == 0;
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return ret;
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};
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if(!IsScalarPerVectorValid(p_arg_->gammaStrides_.back() == 1, GammaSrcVectorSize))
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return false;
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if(!IsScalarPerVectorValid(p_arg_->betaStrides_.back() == 1, BetaSrcVectorSize))
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return false;
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return true;
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};
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std::unique_ptr<BaseArgument> MakeArgumentPointer(const std::vector<index_t> lengths,
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const std::vector<index_t> xStrides,
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const std::vector<index_t> gammaStrides,
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const std::vector<index_t> betaStrides,
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const std::vector<index_t> reduceDims,
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AccDataType epsilon,
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const void* p_x,
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const void* p_gamma,
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const void* p_beta,
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void* p_y,
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AccElementwiseOperation acc_elementwise_op)
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{
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return std::make_unique<Argument>(lengths,
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xStrides,
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gammaStrides,
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betaStrides,
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reduceDims,
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acc_elementwise_op,
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epsilon,
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static_cast<const XDataType*>(p_x),
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static_cast<const GammaDataType*>(p_gamma),
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static_cast<const BetaDataType*>(p_beta),
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static_cast<YDataType*>(p_y));
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};
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std::unique_ptr<BaseInvoker> MakeInvokerPointer() { return std::make_unique<Invoker>(); };
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std::string GetTypeString() const override
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{
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auto str = std::stringstream();
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// clang-format off
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str << "DeviceLayernorm<" << BlockSize << ",";
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str << "M_C" << MThreadClusterSize << "_S" << MThreadSliceSize << ",";
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str << "K_C" << KThreadClusterSize << "_S" << KThreadSliceSize << ",";
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str << "K_C" << KThreadClusterSize << "_S" << KThreadSliceSize << ",";
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str << "XYSrcVectorDim_" << XYSrcVectorDim << ",";
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str << "VectorSize_X" << XSrcVectorSize << "_Gamma" << GammaSrcVectorSize << "_Beta" << BetaSrcVectorSize << "_Y" << YDstVectorSize << ">";
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// clang-format on
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return str.str();
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}
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};
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} // namespace device
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} // namespace tensor_operation
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} // namespace ck
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