mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-16 10:59:55 +00:00
Merge commit '8a0d659f92897e1ae99e4dc0ea4842a2c78170ab' into develop
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@@ -51,7 +51,8 @@ std::ostream& LogRangeAsType(std::ostream& os, Range&& range, std::string delim)
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{
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os << ck::type_convert<float>(v);
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}
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else if constexpr(std::is_same_v<RangeType, ck::pk_i4_t>)
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else if constexpr(std::is_same_v<RangeType, ck::pk_i4_t> ||
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std::is_same_v<RangeType, ck::f4x2_pk_t>)
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{
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const auto packed_floats = ck::type_convert<ck::float2_t>(v);
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const ck::vector_type<float, 2> vector_of_floats{packed_floats};
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@@ -359,7 +360,8 @@ struct Tensor
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std::size_t GetElementSpaceSize() const
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{
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t>)
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t> ||
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ck::is_same_v<ck::remove_cvref_t<T>, ck::f4x2_pk_t>)
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{
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return (mDesc.GetElementSpaceSize() + 1) / 2;
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}
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@@ -514,7 +516,8 @@ struct Tensor
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template <typename... Is>
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std::size_t GetOffsetFromMultiIndex(Is... is) const
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{
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t>)
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t> ||
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ck::is_same_v<ck::remove_cvref_t<T>, ck::f4x2_pk_t>)
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{
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return mDesc.GetOffsetFromMultiIndex(is...) / 2;
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}
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@@ -527,7 +530,8 @@ struct Tensor
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template <typename... Is>
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T& operator()(Is... is)
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{
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t>)
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t> ||
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ck::is_same_v<ck::remove_cvref_t<T>, ck::f4x2_pk_t>)
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{
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return mData[mDesc.GetOffsetFromMultiIndex(is...) / 2];
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}
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@@ -540,7 +544,8 @@ struct Tensor
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template <typename... Is>
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const T& operator()(Is... is) const
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{
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t>)
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t> ||
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ck::is_same_v<ck::remove_cvref_t<T>, ck::f4x2_pk_t>)
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{
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return mData[mDesc.GetOffsetFromMultiIndex(is...) / 2];
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}
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@@ -552,7 +557,8 @@ struct Tensor
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T& operator()(std::vector<std::size_t> idx)
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{
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t>)
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t> ||
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ck::is_same_v<ck::remove_cvref_t<T>, ck::f4x2_pk_t>)
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{
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return mData[mDesc.GetOffsetFromMultiIndex(idx) / 2];
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}
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@@ -564,7 +570,8 @@ struct Tensor
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const T& operator()(std::vector<std::size_t> idx) const
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{
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t>)
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if constexpr(ck::is_same_v<ck::remove_cvref_t<T>, ck::pk_i4_t> ||
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ck::is_same_v<ck::remove_cvref_t<T>, ck::f4x2_pk_t>)
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{
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return mData[mDesc.GetOffsetFromMultiIndex(idx) / 2];
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}
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@@ -1,5 +1,5 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2024, Advanced Micro Devices, Inc. All rights reserved.
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// Copyright (c) 2018-2025, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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@@ -81,6 +81,18 @@ struct GeneratorTensor_1<ck::f4_t>
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}
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};
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template <>
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struct GeneratorTensor_1<ck::f4x2_pk_t>
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{
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float value = 1.0;
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template <typename... Is>
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ck::f4x2_pk_t operator()(Is...)
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{
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return ck::f4x2_pk_t{ck::type_convert<ck::f4x2_t>(ck::float2_t{value, value})};
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}
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};
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template <>
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struct GeneratorTensor_1<int8_t>
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{
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@@ -209,6 +221,21 @@ struct GeneratorTensor_2<ck::f4_t>
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}
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};
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template <>
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struct GeneratorTensor_2<ck::f4x2_pk_t>
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{
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int min_value = 0;
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int max_value = 1;
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template <typename... Is>
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ck::f4x2_pk_t operator()(Is...)
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{
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float tmp0 = (std::rand() % (max_value - min_value)) + min_value;
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float tmp1 = (std::rand() % (max_value - min_value)) + min_value;
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return ck::f4x2_pk_t{ck::type_convert<ck::f4x2_t>(ck::float2_t{tmp0, tmp1})};
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}
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};
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template <typename T>
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struct GeneratorTensor_3
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{
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@@ -296,6 +323,25 @@ struct GeneratorTensor_3<ck::f4_t>
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}
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};
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template <>
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struct GeneratorTensor_3<ck::f4x2_pk_t>
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{
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float min_value = 0;
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float max_value = 1;
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template <typename... Is>
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ck::f4x2_pk_t operator()(Is...)
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{
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float tmp0 = float(std::rand()) / float(RAND_MAX);
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float tmp1 = float(std::rand()) / float(RAND_MAX);
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float fp32_tmp0 = min_value + tmp0 * (max_value - min_value);
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float fp32_tmp1 = min_value + tmp1 * (max_value - min_value);
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return ck::f4x2_pk_t{ck::type_convert<ck::f4x2_t>(ck::float2_t{fp32_tmp0, fp32_tmp1})};
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}
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};
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template <typename T>
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struct GeneratorTensor_4
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{
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@@ -508,6 +508,34 @@ struct intrin_mfma_f32_32x32x64f8f6f4<32, 32>
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ignore = reg_a;
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ignore = reg_b;
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ignore = reg_c;
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#endif
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}
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template <class FloatC>
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__device__ static void Run(const f4x32_t& reg_a, const f4x32_t& reg_b, FloatC& reg_c)
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{
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#if defined(__gfx950__)
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int32x4_t arg_a = bit_cast<int32x4_t>(reg_a);
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int32x4_t arg_b = bit_cast<int32x4_t>(reg_b);
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using arg_type = int32x8_t;
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reg_c.template AsType<float16_t>()(Number<0>{}) =
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__builtin_amdgcn_mfma_scale_f32_32x32x64_f8f6f4(
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arg_type{arg_a[0], arg_a[1], arg_a[2], arg_a[3], 0, 0, 0, 0},
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arg_type{arg_b[0], arg_b[1], arg_b[2], arg_b[3], 0, 0, 0, 0},
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reg_c.template AsType<float16_t>()[Number<0>{}],
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4, // cbsz
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4, // blgp
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0, // OPSEL
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0,
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0, // OPSEL
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0);
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#else
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ignore = reg_a;
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ignore = reg_b;
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ignore = reg_c;
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#endif
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}
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};
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@@ -589,6 +617,40 @@ struct intrin_mfma_scale_f32_32x32x64f8f6f4<32, 32>
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ignore = reg_b;
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ignore = scale_b;
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ignore = reg_c;
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#endif
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}
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template <class FloatC>
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__device__ static void Run(const f4x32_t& reg_a,
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const int32_t scale_a,
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const f4x32_t& reg_b,
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const int32_t scale_b,
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FloatC& reg_c)
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{
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#if defined(__gfx950__)
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int32x4_t arg_a = bit_cast<int32x4_t>(reg_a);
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int32x4_t arg_b = bit_cast<int32x4_t>(reg_b);
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using arg_type = int32x8_t;
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reg_c.template AsType<float16_t>()(Number<0>{}) =
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__builtin_amdgcn_mfma_scale_f32_32x32x64_f8f6f4(
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arg_type{arg_a[0], arg_a[1], arg_a[2], arg_a[3], 0, 0, 0, 0},
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arg_type{arg_b[0], arg_b[1], arg_b[2], arg_b[3], 0, 0, 0, 0},
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reg_c.template AsType<float16_t>()[Number<0>{}],
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4, // cbsz
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4, // blgp
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0, // OPSEL
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scale_a,
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0, // OPSEL
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scale_b);
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#else
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ignore = reg_a;
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ignore = scale_a;
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ignore = reg_b;
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ignore = scale_b;
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ignore = reg_c;
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#endif
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}
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};
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@@ -686,6 +748,39 @@ struct intrin_mfma_scale_f32_16x16x128f8f6f4<16, 16>
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#endif
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}
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template <class FloatC>
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__device__ static void Run(const f4x32_t& reg_a,
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const int32_t scale_a,
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const f4x32_t& reg_b,
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const int32_t scale_b,
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FloatC& reg_c)
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{
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#if defined(__gfx950__)
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int32x4_t arg_a = bit_cast<int32x4_t>(reg_a);
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int32x4_t arg_b = bit_cast<int32x4_t>(reg_b);
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using arg_type = int32x8_t;
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reg_c.template AsType<float4_t>()(Number<0>{}) =
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__builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4(
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arg_type{arg_a[0], arg_a[1], arg_a[2], arg_a[3], 0, 0, 0, 0},
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arg_type{arg_b[0], arg_b[1], arg_b[2], arg_b[3], 0, 0, 0, 0},
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reg_c.template AsType<float4_t>()[Number<0>{}],
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4, // cbsz
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4, // blgp
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0, // OPSEL
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scale_a,
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0, // OPSEL
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scale_b);
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#else
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ignore = reg_a;
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ignore = scale_a;
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ignore = reg_b;
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ignore = scale_b;
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ignore = reg_c;
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#endif
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}
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template <class FloatC>
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__device__ static void Run(const bf8x32_t& reg_a,
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const int32_t& scale_a,
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@@ -748,6 +843,33 @@ struct intrin_mfma_f32_16x16x128f8f6f4<16, 16>
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ignore = reg_a;
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ignore = reg_b;
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ignore = reg_c;
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#endif
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}
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template <class FloatC>
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__device__ static void Run(const f4x32_t& reg_a, const f4x32_t& reg_b, FloatC& reg_c)
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{
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#if defined(__gfx950__)
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int32x4_t arg_a = bit_cast<int32x4_t>(reg_a);
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int32x4_t arg_b = bit_cast<int32x4_t>(reg_b);
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using arg_type = int32x8_t;
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reg_c.template AsType<float4_t>()(Number<0>{}) =
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__builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4(
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arg_type{arg_a[0], arg_a[1], arg_a[2], arg_a[3], 0, 0, 0, 0},
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arg_type{arg_b[0], arg_b[1], arg_b[2], arg_b[3], 0, 0, 0, 0},
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reg_c.template AsType<float4_t>()[Number<0>{}],
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4, // cbsz
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4, // blgp
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0, // OPSEL
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0,
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0, // OPSEL
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0);
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#else
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ignore = reg_a;
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ignore = reg_b;
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ignore = reg_c;
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#endif
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}
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};
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@@ -470,6 +470,13 @@ struct scalar_type<e8m0_bexp_t>
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static constexpr index_t vector_size = 1;
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};
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template <>
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struct scalar_type<f4x2_pk_t>
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{
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using type = f4x2_pk_t::type;
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static constexpr index_t vector_size = 1;
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};
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template <>
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struct scalar_type<bool>
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{
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