mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-04-19 22:39:03 +00:00
[CK_BUILDER] Add reflection for wmma and bwd weight instances to ck builder reflection (#3592)
* added reflection for conv_fwd_multiple_d_wmma_cshuffle.hpp * added reflection for device_grouped_conv_bwd_weight_xdl_cshuffle * added reflection for device_grouped_conv_bwd_weight_xdl_cshuffle v3 * added reflection of max_transpose parameters * fix printing of std optional parameters * fix use of undefined ck::index * added conv traits for device_grouped_conv_bwd_weight_multiple_d_xdl_cshuffle * added xdl two stage instance to reflection * added additional variables * added reflection for grouped_conv_bwd_weight_multiple_d_wmma_cshuffle, _v3, grouped_conv_two_stage_wmma_cshuffle_v3, * added reflection for device_grouped_conv_bwd_weigh_wmma_cshuffle_v3 * added reflection for bwd_weight_wmma_cshuffle * added comments back in * add printed output for optional parameters * update README * fix typo * added num_gemm_k_prefetch_stage and small fixes * modified test string due to reflection of new parameter --------- Co-authored-by: Kevin Abraham <kevin.abraham@streamhpc.com>
This commit is contained in:
kabrahamAMD
@@ -259,9 +259,118 @@ TEST(ConvDescriptionTest, DefaultInstanceHasDetailedDescription)
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static constexpr const ConvSignature SIGNATURE;
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static constexpr const DefaultAlgorithm ALGORITHM;
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using Instance = ckb::ConvBuilder<SIGNATURE, ALGORITHM>::Instance;
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EXPECT_THAT(
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ckr::describe<Instance>().detailed(),
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ckt::StringEqWithDiff( //
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"2D Forward Convolution Kernel\n"
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"├─ Signature\n"
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"│ ├─ Tensor Type: FP16\n"
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"│ ├─ Input Layout: GNHWC\n"
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"│ ├─ Weight Layout: GKYXC\n"
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"│ ├─ Output Layout: GNHWK\n"
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"│ ├─ Input elementwise operation: PASS_THROUGH\n"
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"│ ├─ Weights elementwise operation: PASS_THROUGH\n"
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"│ └─ Output elementwise operation: PASS_THROUGH\n"
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"└─ Algorithm\n"
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" ├─ Thread block size: 256\n"
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" ├─ Data tile size: 256×256×32\n"
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" ├─ Gemm padding: DEFAULT\n"
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" ├─ Convolution specialization: DEFAULT\n"
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" ├─ Pipeline version: V4\n"
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" ├─ Pipeline scheduler: INTRAWAVE\n"
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" ├─ Warp Gemm parameters: \n"
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" │ ├─ subtile size: 16×16\n"
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" │ └─ Number of warp gemm iterations: 8×8\n"
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" └─ Memory access:\n"
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" ├─ A Tile transfer: \n"
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" │ ├─ Tile dimensions: 4×256×8×\n"
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" │ ├─ The innermost K subdimension size: 8\n"
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" │ ├─ Spatial thread distribution over the data tile: 0×1×2\n"
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" │ ├─ The order of accessing data tile axes: 0×1×2\n"
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" │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 2\n"
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" │ ├─ Vector access (LDS write) instruction size: 2\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 2\n"
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" ├─ B Tile transfer: \n"
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" │ ├─ Tile dimensions: 4×256×8×\n"
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" │ ├─ The innermost K subdimension size: 8\n"
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" │ ├─ Spatial thread distribution over the data tile: 0×1×2\n"
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" │ ├─ The order of accessing data tile axes: 0×1×2\n"
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" │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 2\n"
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" │ ├─ Vector access (LDS write) instruction size: 2\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 2\n"
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" └─ C Tile transfer: \n"
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" ├─ Data shuffle (number of gemm instructions per iteration): 1×1\n"
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" ├─ Spatial thread distribution used to store data: 1×32×1×8\n"
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" ├─ Vector access (GMEM write) instruction size: 2\n"
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" ├─ Struct does not contain optional num_gemm_k_prefetch_stage parameter\n"
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" ├─ Struct does not contain optional max_transpose_transfer_src_scalar_per_vector "
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"parameter\n"
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" ├─ Struct does not contain optional max_transpose_dst_scalar_per_vector parameter\n"
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" └─ Struct does not contain optional num_groups_to_merge parameter"));
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}
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// Test printing of optional parameters num_groups_to_merge,
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// nax_transose_transfer_src_scalar_per_vector and max_transpose_dst_scalar_per_vector
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TEST(ConvDescriptionTest, BwdWeightTwoStageWmmaV3DescriptionTest)
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{
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using Instance =
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ck::tensor_operation::device::DeviceGroupedConvBwdWeightTwoStage_Wmma_CShuffleV3<
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2, // NDimSpatial
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ck::tensor_layout::convolution::GNHWC, // InLayout
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ck::tensor_layout::convolution::GKYXC, // WeiLayout
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ck::tensor_layout::convolution::GNHWK, // OutLayout
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ck::half_t, // InDataType
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ck::half_t, // WeiDataType
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ck::half_t, // OutDataType
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float, // AccDataType
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ck::tensor_operation::element_wise::PassThrough, // InElementwiseOperation
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ck::tensor_operation::element_wise::PassThrough, // WeiElementwiseOperation
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ck::tensor_operation::element_wise::PassThrough, // OutElementwiseOperation
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ck::tensor_operation::device::ConvolutionBackwardWeightSpecialization::
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Default, // ConvBackwardWeightSpecialization
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256, // BlockSize
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128, // MPerBlock
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128, // NPerBlock
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16, // K0PerBlock
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8, // AK1
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32, // MPerWMMA
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32, // NPerXDL
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4, // MRepeat
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4, // NRepeat
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ck::Sequence<4, 64, 1>, // ABlockTransferThreadClusterLengths_AK0_M_AK1
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ck::Sequence<1, 0, 2>, // ABlockTransferThreadClusterArrangeOrder_
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ck::Sequence<1, 0, 2>, // ABlockTransferSrcAccessOrder
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2, // ABlockTransferSrcVectorDim
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8, // ABlockTransferSrcScalarPerVector
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8, // ABlockTransferDstScalarPerVector_K1
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1, // ABlockLdsAddExtraM
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ck::Sequence<4, 64, 1>, // BBlockTransferThreadClusterLengths_BK0_N_BK1
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ck::Sequence<1, 0, 2>, // BBlockTransferThreadClusterArrangeOrder_
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ck::Sequence<1, 0, 2>, // BBlockTransferSrcAccessOrder_
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2, // BBlockTransferSrcVectorDim
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8, // BBlockTransferSrcScalarPerVector
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8, // BBlockTransferDstScalarPerVector_K1
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1, // BBlockLdsAddExtraN
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1, // CShuffleMXdlPerWavePerShuffle
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1, // CShuffleNXdlPerWavePerShuffle
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ck::Sequence<1,
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32,
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1,
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8>, // CBlockTransferClusterLengths_MBlock_MPerBlock_NBlock_NPerBlock_
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8, // CDEBlockTransferScalarPerVector_NPerBlock_
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ck::BlockGemmPipelineScheduler::Intrawave, // BlkGemmPipeSched
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ck::BlockGemmPipelineVersion::v1, // BlkGemmPipelineVer
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4, // NumGroupsToMerge
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ck::half_t, // AComputeDataType
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ck::half_t, // BComputeDataType
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1, // MaxTransposeTransferSrcScalarPerVector
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1>; // MaxTransposeTransferDstScalarPerVector>
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EXPECT_THAT(ckr::describe<Instance>().detailed(),
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ckt::StringEqWithDiff( //
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"2D Forward Convolution Kernel\n"
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"2D Backward Weight Convolution Kernel\n"
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"├─ Signature\n"
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"│ ├─ Tensor Type: FP16\n"
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"│ ├─ Input Layout: GNHWC\n"
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@@ -272,37 +381,146 @@ TEST(ConvDescriptionTest, DefaultInstanceHasDetailedDescription)
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"│ └─ Output elementwise operation: PASS_THROUGH\n"
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"└─ Algorithm\n"
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" ├─ Thread block size: 256\n"
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" ├─ Data tile size: 256×256×32\n"
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" ├─ Gemm padding: DEFAULT\n"
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" ├─ Data tile size: 128×128×16\n"
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" ├─ Struct does not contain optional gemm_padding argument\n"
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" ├─ Convolution specialization: DEFAULT\n"
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" ├─ Pipeline version: V4\n"
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" ├─ Pipeline scheduler: INTRAWAVE\n"
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" ├─ Pipeline version: V1\n"
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" ├─ Pipeline scheduler: DEFAULT\n"
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" ├─ Warp Gemm parameters: \n"
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" │ ├─ subtile size: 16×16\n"
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" │ └─ Number of warp gemm iterations: 8×8\n"
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" │ ├─ subtile size: 32×32\n"
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" │ └─ Number of warp gemm iterations: 4×4\n"
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" └─ Memory access:\n"
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" ├─ A Tile transfer: \n"
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" │ ├─ Tile dimensions: 4×256×8×\n"
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" │ ├─ Tile dimensions: 2×128×8×\n"
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" │ ├─ The innermost K subdimension size: 8\n"
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" │ ├─ Spatial thread distribution over the data tile: 0×1×2\n"
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" │ ├─ The order of accessing data tile axes: 0×1×2\n"
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" │ ├─ Spatial thread distribution over the data tile: 1×0×2\n"
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" │ ├─ The order of accessing data tile axes: 1×0×2\n"
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" │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 2\n"
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" │ ├─ Vector access (LDS write) instruction size: 2\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 8\n"
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" │ ├─ Vector access (LDS write) instruction size: 8\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 8\n"
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" ├─ B Tile transfer: \n"
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" │ ├─ Tile dimensions: 4×256×8×\n"
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" │ ├─ Tile dimensions: 2×128×8×\n"
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" │ ├─ The innermost K subdimension size: 8\n"
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" │ ├─ Spatial thread distribution over the data tile: 0×1×2\n"
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" │ ├─ The order of accessing data tile axes: 0×1×2\n"
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" │ ├─ Spatial thread distribution over the data tile: 1×0×2\n"
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" │ ├─ The order of accessing data tile axes: 1×0×2\n"
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" │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 2\n"
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" │ ├─ Vector access (LDS write) instruction size: 2\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 8\n"
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" │ ├─ Vector access (LDS write) instruction size: 8\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 8\n"
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" └─ C Tile transfer: \n"
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" ├─ Data shuffle (number of gemm instructions per iteration): 1×1\n"
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" ├─ Spatial thread distribution used to store data: 1×32×1×8\n"
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" └─ Vector access (GMEM write) instruction size: 2"));
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" ├─ Vector access (GMEM write) instruction size: 8\n"
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" ├─ Struct does not contain optional num_gemm_k_prefetch_stage parameter\n"
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" ├─ Max Transpose transfer scr scalar per vector: 1\n"
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" ├─ Max Transpose dst scalar per vector: 1\n"
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" └─ Num groups to merge: 4"));
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}
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// Test printing of optional parameters num_groups_to_merge,
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// nax_transose_transfer_src_scalar_per_vector and max_transpose_dst_scalar_per_vector
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TEST(ConvDescriptionTest, BwdWeightWmmaCshuffleV3DescriptionTest)
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{
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using Instance = ck::tensor_operation::device::DeviceGroupedConvBwdWeight_Wmma_CShuffle<
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3, // NDimSpatial
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ck::tensor_layout::convolution::GNDHWC, // InLayout
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ck::tensor_layout::convolution::GKZYXC, // WeiLayout
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ck::tensor_layout::convolution::GNDHWK, // OutLayout
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ck::half_t, // InDataType
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ck::half_t, // WeiDataType
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ck::half_t, // OutDataType
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float, // AccDataType
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ck::tensor_operation::element_wise::PassThrough, // InElementwiseOperation
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ck::tensor_operation::element_wise::PassThrough, // WeiElementwiseOperation
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ck::tensor_operation::element_wise::PassThrough, // OutElementwiseOperation
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ck::tensor_operation::device::ConvolutionBackwardWeightSpecialization::
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Default, // ConvBackwardWeightSpecialization
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256, // BlockSize
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128, // MPerBlock
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128, // NPerBlock
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16, // K0PerBlock
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8, // K1
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32, // MPerWmma
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32, // NPerWmma
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4, // MRepeat
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4, // NRepeat
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ck::Sequence<4, 64, 1>, // ABlockTransferThreadClusterLengths_K0_M_K1
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ck::Sequence<1, 0, 2>, // ABlockTransferThreadClusterArrangeOrder_
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ck::Sequence<1, 0, 2>, // ABlockTransferSrcAccessOrder
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2, // ABlockTransferSrcVectorDim
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8, // ABlockTransferSrcScalarPerVector
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8, // ABlockTransferDstScalarPerVector_K1
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1, // ABlockLdsAddExtraM
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ck::Sequence<4, 64, 1>, // BBlockTransferThreadClusterLengths_K0_N_K1
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ck::Sequence<1, 0, 2>, // BBlockTransferThreadClusterArrangeOrder_
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ck::Sequence<1, 0, 2>, // BBlockTransferSrcAccessOrder_
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2, // BBlockTransferSrcVectorDim
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8, // BBlockTransferSrcScalarPerVector
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8, // BBlockTransferDstScalarPerVector_K1
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1, // BBlockLdsAddExtraN
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1, // CShuffleMXdlPerWavePerShuffle
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1, // CShuffleNXdlPerWavePerShuffle
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ck::Sequence<1,
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32,
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1,
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8>, // CBlockTransferClusterLengths_MBlock_MPerBlock_NBlock_NPerBlock_
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8, // CDEBlockTransferScalarPerVector_NPerBlock_
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1, // NummGemmKPrefetchStage
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ck::LoopScheduler::Default, // BlkGemmPipeSched
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ck::PipelineVersion::v1, // BlkGemmPipelineVer
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false>; // BComputeDataType
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EXPECT_THAT(
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ckr::describe<Instance>().detailed(),
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ckt::StringEqWithDiff( //
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"3D Backward Weight Convolution Kernel\n"
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"├─ Signature\n"
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"│ ├─ Tensor Type: FP16\n"
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"│ ├─ Input Layout: GNDHWC\n"
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"│ ├─ Weight Layout: GKZYXC\n"
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"│ ├─ Output Layout: GNDHWK\n"
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"│ ├─ Input elementwise operation: PASS_THROUGH\n"
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"│ ├─ Weights elementwise operation: PASS_THROUGH\n"
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"│ └─ Output elementwise operation: PASS_THROUGH\n"
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"└─ Algorithm\n"
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" ├─ Thread block size: 256\n"
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" ├─ Data tile size: 128×128×16\n"
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" ├─ Struct does not contain optional gemm_padding argument\n"
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" ├─ Convolution specialization: DEFAULT\n"
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" ├─ Pipeline version: V1\n"
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" ├─ Pipeline scheduler: DEFAULT\n"
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" ├─ Warp Gemm parameters: \n"
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" │ ├─ subtile size: 32×32\n"
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" │ └─ Number of warp gemm iterations: 4×4\n"
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" └─ Memory access:\n"
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" ├─ A Tile transfer: \n"
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" │ ├─ Tile dimensions: 2×128×8×\n"
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" │ ├─ The innermost K subdimension size: 8\n"
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" │ ├─ Spatial thread distribution over the data tile: 1×0×2\n"
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" │ ├─ The order of accessing data tile axes: 1×0×2\n"
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" │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 8\n"
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" │ ├─ Vector access (LDS write) instruction size: 8\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 8\n"
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" ├─ B Tile transfer: \n"
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" │ ├─ Tile dimensions: 2×128×8×\n"
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" │ ├─ The innermost K subdimension size: 8\n"
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" │ ├─ Spatial thread distribution over the data tile: 1×0×2\n"
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" │ ├─ The order of accessing data tile axes: 1×0×2\n"
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" │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 8\n"
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" │ ├─ Vector access (LDS write) instruction size: 8\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 8\n"
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" └─ C Tile transfer: \n"
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" ├─ Data shuffle (number of gemm instructions per iteration): 1×1\n"
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" ├─ Spatial thread distribution used to store data: 1×32×1×8\n"
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" ├─ Vector access (GMEM write) instruction size: 8\n"
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" ├─ Num gemm k prefetch stage: 1\n"
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" ├─ Struct does not contain optional max_transpose_transfer_src_scalar_per_vector "
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"parameter\n"
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" ├─ Struct does not contain optional max_transpose_dst_scalar_per_vector parameter\n"
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" └─ Struct does not contain optional num_groups_to_merge parameter"));
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}
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TEST(ConvDescriptionTest, DefaultInstanceHasInstanceString)
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