mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-04 05:31:24 +00:00
Add batched/grouped_gemm contraction deviceOps (#349)
* convnd_fwd fp16 example * update example * update example * update instance * updating refernce conv * update reference conv * update conv fwd profiler * update conv 1d and 3d instance * update include path * clean * update profiler for conv bwd data and weight * update conv bwd weight * clean * update conv example * update profiler for conv bwd weight * update ckprofiler for conv bwd data * fix reference conv bwd data bug; update conv bwd data test * update examples * fix initialization issue * update test for conv fwd * clean * clean * remove test case too sensitive to error threshhold * fix test * clean * fix build * adding conv multiple d * adding conv multiple D * add matrix padder * add gemm padding to convnd * adding group conv * update gemm multi-d * refactor * refactor * refactor * clean * clean * refactor * refactor * reorg * add ds * add bias * clean * add G * adding group * adding group * adding group * update Tensor * clean * update example * update DeviceGemmMultipleD_Xdl_CShuffle * update conv bwd-data and bwd-weight * upate contraction example * update gemm and batch gemm with e permute * fix example build * instance for grouped conv1d * update example * adding group conv instance * update gemm bilinear instance * update gemm+add+add+fastgelu instance * update profiler * update profiler * update test * update test and client example * clean * add grouped conv into profiler * update profiler * clean * add test grouped conv, update all conv test to gtest * update test * change gemm_c_permute with contraction * add grouped_contraction * add contraction in group_gemm * add example of grouped_gemm with contraction * add example of grouped_contraction_bias_e_permute * clean * fixed ds * add m3n2 m2n3 examples into gemm_bias_e_permute Co-authored-by: Chao Liu <chao.liu2@amd.com>
This commit is contained in:
zjing14
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2022, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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#include <iostream>
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#include <vector>
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#include "ck/tensor_operation/gpu/device/device_base.hpp"
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namespace ck {
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namespace tensor_operation {
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namespace device {
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// Tensor Contraction:
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// input : A
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// input : B
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// input : D0, D1, ...
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// output : E
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// C = a_op(A) * b_op(B)
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// E = cde_op(C, D0, D1, ...)
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// Assume:
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// A[G0, G1, ..., M0, M1, M2, ..., K0, K1, K2, ...]
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// B[G0, G1, ..., N0, N1, N2, ..., K0, K1, K2, ...]
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// D[G0, G1, ..., M0, M1, M2, ..., N0, N1, N2, ...]
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// E[G0, G1, ..., M0, M1, M2, ..., N0, N1, N2, ...]
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template <index_t NumDimG,
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index_t NumDimM,
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index_t NumDimN,
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index_t NumDimK,
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typename ADataType,
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typename BDataType,
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typename DsDataType,
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typename EDataType,
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typename AElementwiseOperation,
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typename BElementwiseOperation,
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typename CDEElementwiseOperation>
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struct DeviceBatchedContractionMultipleD : public BaseOperator
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{
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static constexpr index_t NumDTensor = DsDataType::Size();
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virtual std::unique_ptr<BaseArgument>
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MakeArgumentPointer(const void* p_a,
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const void* p_b,
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std::array<const void*, NumDTensor> p_ds,
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void* p_e,
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const std::vector<index_t>& a_gs_ms_ns_lengths,
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const std::vector<index_t>& a_gs_ms_ks_strides,
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const std::vector<index_t>& b_gs_ns_ks_lengths,
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const std::vector<index_t>& b_gs_ns_ks_strides,
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const std::array<std::vector<index_t>, NumDTensor>& ds_gs_ms_ns_lengths,
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const std::array<std::vector<index_t>, NumDTensor>& ds_gs_ms_ns_strides,
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const std::vector<index_t>& e_gs_ms_ns_lengths,
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const std::vector<index_t>& e_gs_ms_ns_strides,
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AElementwiseOperation a_element_op,
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BElementwiseOperation b_element_op,
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CDEElementwiseOperation cde_element_op) = 0;
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virtual std::unique_ptr<BaseInvoker> MakeInvokerPointer() = 0;
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};
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} // namespace device
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} // namespace tensor_operation
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} // namespace ck
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File diff suppressed because it is too large
Load Diff
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2022, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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#include <iostream>
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#include <vector>
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#include "ck/tensor_operation/gpu/device/device_base.hpp"
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namespace ck {
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namespace tensor_operation {
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namespace device {
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template <index_t NumDTensor>
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struct ContractionDesc
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{
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std::vector<index_t> a_ms_ks_lengths;
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std::vector<index_t> a_ms_ks_strides;
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std::vector<index_t> b_ns_ks_lengths;
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std::vector<index_t> b_ns_ks_strides;
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std::array<std::vector<index_t>, NumDTensor> ds_ms_ns_lengths;
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std::array<std::vector<index_t>, NumDTensor> ds_ms_ns_strides;
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std::vector<index_t> e_ms_ns_lengths;
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std::vector<index_t> e_ms_ns_strides;
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};
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// Tensor Contraction:
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// input : A
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// input : B
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// input : D0, D1, ...
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// output : E
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// C = a_op(A) * b_op(B)
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// E = cde_op(C, D0, D1, ...)
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// Assume:
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// A[M0, M1, M2, ..., K0, K1, K2, ...]
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// B[N0, N1, N2, ..., K0, K1, K2, ...]
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// D[M0, M1, M2, ..., N0, N1, N2, ...]
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// E[M0, M1, M2, ..., N0, N1, N2, ...]
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template <index_t NumDimM,
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index_t NumDimN,
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index_t NumDimK,
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typename ADataType,
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typename BDataType,
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typename DsDataType,
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typename EDataType,
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typename AElementwiseOperation,
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typename BElementwiseOperation,
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typename CDEElementwiseOperation>
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struct DeviceGroupedContractionMultipleD : public BaseOperator
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{
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static constexpr index_t NumDTensor = DsDataType::Size();
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virtual std::unique_ptr<BaseArgument>
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MakeArgumentPointer(std::vector<const void*> p_a_vec,
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std::vector<const void*> p_b_vec,
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std::vector<std::array<const void*, NumDTensor>> p_ds_vec,
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std::vector<void*> p_e_vec,
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std::vector<ContractionDesc<NumDTensor>> contraction_descs,
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AElementwiseOperation a_element_op,
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BElementwiseOperation b_element_op,
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CDEElementwiseOperation cde_element_op) = 0;
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virtual std::unique_ptr<BaseInvoker> MakeInvokerPointer() = 0;
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};
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} // namespace device
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} // namespace tensor_operation
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} // namespace ck
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@@ -0,0 +1,908 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2022, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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#include <iostream>
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#include <sstream>
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#include "ck/utility/common_header.hpp"
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#include "ck/tensor_description/tensor_descriptor.hpp"
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#include "ck/tensor_description/tensor_descriptor_helper.hpp"
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#include "ck/tensor_operation/gpu/device/tensor_layout.hpp"
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#include "ck/tensor_operation/gpu/device/device_grouped_contraction_multiple_d.hpp"
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#include "ck/tensor_operation/gpu/device/gemm_specialization.hpp"
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#include "ck/tensor_operation/gpu/device/tensor_specialization.hpp"
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#include "ck/tensor_operation/gpu/device/matrix_padder.hpp"
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#include "ck/tensor_operation/gpu/grid/gridwise_gemm_multiple_d_xdl_cshuffle.hpp"
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#include "ck/host_utility/device_prop.hpp"
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#include "ck/host_utility/kernel_launch.hpp"
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namespace ck {
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template <typename GridwiseGemm,
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typename ContractionMultiDKernelArg,
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typename AElementwiseOperation,
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typename BElementwiseOperation,
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typename CDEElementwiseOperation,
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bool HasMainKBlockLoop>
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__global__ void
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#if CK_USE_LAUNCH_BOUNDS
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__launch_bounds__(CK_MAX_THREAD_PER_BLOCK, CK_MIN_BLOCK_PER_CU)
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#endif
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kernel_grouped_contraction_multiple_d_xdl_cshuffle(
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const void CK_CONSTANT_ADDRESS_SPACE* contraction_args,
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const index_t group_count,
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const AElementwiseOperation a_element_op,
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const BElementwiseOperation b_element_op,
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const CDEElementwiseOperation cde_element_op)
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{
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#if(!defined(__HIP_DEVICE_COMPILE__) || defined(__gfx908__) || defined(__gfx90a__))
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__shared__ char p_shared[GridwiseGemm::GetSharedMemoryNumberOfByte()];
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const index_t block_id = get_block_1d_id();
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const auto contraction_arg_ptr = reinterpret_cast<const ContractionMultiDKernelArg*>(
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cast_pointer_to_generic_address_space(contraction_args));
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index_t left = 0;
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index_t right = group_count;
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index_t group_id = index_t((left + right) / 2);
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while((!(block_id >= contraction_arg_ptr[group_id].block_start_ &&
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block_id < contraction_arg_ptr[group_id].block_end_)) &&
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left <= right)
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{
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if(block_id < contraction_arg_ptr[group_id].block_start_)
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{
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right = group_id;
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}
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else
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{
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left = group_id;
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}
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group_id = index_t((left + right) / 2);
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}
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GridwiseGemm::template Run<HasMainKBlockLoop>(
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contraction_arg_ptr[group_id].p_a_grid_,
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contraction_arg_ptr[group_id].p_b_grid_,
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contraction_arg_ptr[group_id].p_ds_grid_,
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contraction_arg_ptr[group_id].p_e_grid_,
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p_shared,
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a_element_op,
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b_element_op,
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cde_element_op,
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contraction_arg_ptr[group_id].a_grid_desc_ak0_m_ak1_,
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contraction_arg_ptr[group_id].b_grid_desc_bk0_n_bk1_,
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contraction_arg_ptr[group_id].ds_grid_desc_mblock_mperblock_nblock_nperblock_,
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contraction_arg_ptr[group_id].e_grid_desc_mblock_mperblock_nblock_nperblock_,
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contraction_arg_ptr[group_id].block_2_etile_map_);
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#else
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ignore = contraction_args;
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ignore = group_count;
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ignore = a_element_op;
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ignore = b_element_op;
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ignore = cde_element_op;
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#endif
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}
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} // namespace ck
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namespace ck {
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namespace tensor_operation {
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namespace device {
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// Tensor Contraction:
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// input : A
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// input : B
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// input : D0, D1, ...
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// output : E
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// C = a_op(A) * b_op(B)
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// E = cde_op(C, D0, D1, ...)
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// Assume:
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// A[M0, M1, M2, ..., K0, K1, K2, ...]
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// B[N0, N1, N2, ..., K0, K1, K2, ...]
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// D[M0, M1, M2, ..., N0, N1, N2, ...]
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// E[M0, M1, M2, ..., N0, N1, N2, ...]
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template <index_t NumDimM,
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index_t NumDimN,
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index_t NumDimK,
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typename ADataType,
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typename BDataType,
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typename AccDataType,
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typename CShuffleDataType,
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typename DsDataType,
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typename EDataType,
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typename AElementwiseOperation,
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typename BElementwiseOperation,
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typename CDEElementwiseOperation,
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GemmSpecialization GemmSpec,
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TensorSpecialization ASpec,
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TensorSpecialization BSpec,
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TensorSpecialization DESpec,
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index_t NumGemmKPrefetchStage,
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index_t BlockSize,
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index_t MPerBlock,
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index_t NPerBlock,
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index_t KPerBlock,
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index_t AK1,
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index_t BK1,
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index_t MPerXDL,
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index_t NPerXDL,
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index_t MXdlPerWave,
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index_t NXdlPerWave,
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typename ABlockTransferThreadClusterLengths_AK0_M_AK1,
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typename ABlockTransferThreadClusterArrangeOrder,
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typename ABlockTransferSrcAccessOrder,
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index_t ABlockTransferSrcVectorDim,
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index_t ABlockTransferSrcScalarPerVector,
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index_t ABlockTransferDstScalarPerVector_AK1,
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bool ABlockLdsExtraM,
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typename BBlockTransferThreadClusterLengths_BK0_N_BK1,
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typename BBlockTransferThreadClusterArrangeOrder,
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typename BBlockTransferSrcAccessOrder,
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index_t BBlockTransferSrcVectorDim,
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index_t BBlockTransferSrcScalarPerVector,
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index_t BBlockTransferDstScalarPerVector_BK1,
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bool BBlockLdsExtraN,
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index_t CShuffleMXdlPerWavePerShuffle,
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index_t CShuffleNXdlPerWavePerShuffle,
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typename CDEBlockTransferClusterLengths_MBlock_MPerBlock_NBlock_NPerBlock,
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index_t CDEBlockTransferScalarPerVector_NPerBlock,
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LoopScheduler LoopSched = make_default_loop_scheduler()>
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struct DeviceGroupedContractionMultipleD_Xdl_CShuffle
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: public DeviceGroupedContractionMultipleD<NumDimM,
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NumDimN,
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NumDimK,
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ADataType,
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BDataType,
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DsDataType,
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EDataType,
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AElementwiseOperation,
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BElementwiseOperation,
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CDEElementwiseOperation>
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{
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using DeviceOp = DeviceGroupedContractionMultipleD_Xdl_CShuffle;
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static constexpr index_t NumDTensor = DsDataType::Size();
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static constexpr auto I0 = Number<0>{};
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static constexpr auto I1 = Number<1>{};
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static constexpr auto I2 = Number<2>{};
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static constexpr auto I3 = Number<3>{};
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static constexpr auto matrix_padder =
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MatrixPadder<GemmSpec, index_t, index_t, index_t>{MPerBlock, NPerBlock, KPerBlock};
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// Assume: A[M0, M1, M2, ..., K0, K1, K2, ...]
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static auto MakeAGridDescriptor_M_K(const std::vector<index_t>& a_ms_ks_lengths_vec,
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const std::vector<index_t>& a_ms_ks_strides_vec)
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{
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assert(a_ms_ks_lengths_vec.size() == NumDimM + NumDimK &&
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a_ms_ks_strides_vec.size() == NumDimM + NumDimK);
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const auto to_tuple = [&](auto& vec, auto num) {
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return generate_tuple([&](auto i) { return vec[i]; }, num);
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};
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const auto a_ms_ks_lengths = to_tuple(a_ms_ks_lengths_vec, Number<NumDimM + NumDimK>{});
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const auto a_ms_ks_strides = to_tuple(a_ms_ks_strides_vec, Number<NumDimM + NumDimK>{});
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// dimension Ids for M0, M1, ...
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constexpr auto mDimIds = typename arithmetic_sequence_gen<0, NumDimM, 1>::type{};
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// dimension Ids for K0, K1, ...
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constexpr auto kDimIds =
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typename arithmetic_sequence_gen<NumDimM, NumDimM + NumDimK, 1>::type{};
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// lengths for M0, M1, ...
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const auto mLengths = get_container_subset(a_ms_ks_lengths, mDimIds);
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// lengths for K0, K1, ...
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const auto kLengths = get_container_subset(a_ms_ks_lengths, kDimIds);
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if constexpr(ASpec == TensorSpecialization::Packed)
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{
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auto M = container_reduce(mLengths, math::multiplies{}, Number<1>{});
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auto K = container_reduce(kLengths, math::multiplies{}, Number<1>{});
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const auto a_grid_desc_mraw_kraw = make_naive_tensor_descriptor(
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make_tuple(M, K),
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make_tuple(a_ms_ks_strides[Number<NumDimM - 1>{}],
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a_ms_ks_strides[Number<NumDimM + NumDimK - 1>{}]));
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return matrix_padder.PadADescriptor_M_K(a_grid_desc_mraw_kraw);
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}
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else
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{
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// naive tensor A[M0, M1, M2, ..., K0, K1, K2...]
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const auto a_grid_desc_ms_ks =
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make_naive_tensor_descriptor(a_ms_ks_lengths, a_ms_ks_strides);
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// transformed tensor A[MRaw = M0 * M1 * M2 * ... , KRaw = K0 * K1 * K2 * ...]
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const auto a_grid_desc_mraw_kraw = transform_tensor_descriptor(
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a_grid_desc_ms_ks,
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make_tuple(make_merge_transform(mLengths), make_merge_transform(kLengths)),
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make_tuple(mDimIds, kDimIds),
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make_tuple(Sequence<0>{}, Sequence<1>{}));
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return matrix_padder.PadADescriptor_M_K(a_grid_desc_mraw_kraw);
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}
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}
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// Assume: B[N0, N1, N2, ..., K0, K1, K2, ...]
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static auto MakeBGridDescriptor_N_K(const std::vector<index_t>& b_ns_ks_lengths_vec,
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const std::vector<index_t>& b_ns_ks_strides_vec)
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{
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assert(b_ns_ks_lengths_vec.size() == NumDimN + NumDimK &&
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b_ns_ks_strides_vec.size() == NumDimN + NumDimK);
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const auto to_tuple = [&](auto& vec, auto num) {
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return generate_tuple([&](auto i) { return vec[i]; }, num);
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};
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const auto b_ns_ks_lengths = to_tuple(b_ns_ks_lengths_vec, Number<NumDimN + NumDimK>{});
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const auto b_ns_ks_strides = to_tuple(b_ns_ks_strides_vec, Number<NumDimN + NumDimK>{});
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// dimension Ids for N0, N1, ...
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constexpr auto nDimIds = typename arithmetic_sequence_gen<0, NumDimN, 1>::type{};
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// dimension Ids for K0, K1, ...
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constexpr auto kDimIds =
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typename arithmetic_sequence_gen<NumDimN, NumDimN + NumDimK, 1>::type{};
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// lengths for K0, K1, ...
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const auto kLengths = get_container_subset(b_ns_ks_lengths, kDimIds);
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// lengths for N0, N1, ...
|
||||
const auto nLengths = get_container_subset(b_ns_ks_lengths, nDimIds);
|
||||
|
||||
if constexpr(BSpec == TensorSpecialization::Packed)
|
||||
{
|
||||
auto N = container_reduce(nLengths, math::multiplies{}, Number<1>{});
|
||||
auto K = container_reduce(kLengths, math::multiplies{}, Number<1>{});
|
||||
const auto b_grid_desc_nraw_kraw = make_naive_tensor_descriptor(
|
||||
make_tuple(N, K),
|
||||
make_tuple(b_ns_ks_strides[Number<NumDimN - 1>{}],
|
||||
b_ns_ks_strides[Number<NumDimN + NumDimK - 1>{}]));
|
||||
return matrix_padder.PadBDescriptor_N_K(b_grid_desc_nraw_kraw);
|
||||
}
|
||||
else
|
||||
{
|
||||
// naive tensor B[N0, N1, N2, ..., K0, K1, K2, ...]
|
||||
const auto b_grid_desc_ns_ks =
|
||||
make_naive_tensor_descriptor(b_ns_ks_lengths, b_ns_ks_strides);
|
||||
|
||||
// transformed tensor B[NRaw = N0 * N1 * N2 * ..., KRaw = K0 * K1 * K2 * ...]
|
||||
const auto b_grid_desc_nraw_kraw = transform_tensor_descriptor(
|
||||
b_grid_desc_ns_ks,
|
||||
make_tuple(make_merge_transform(nLengths), make_merge_transform(kLengths)),
|
||||
make_tuple(nDimIds, kDimIds),
|
||||
make_tuple(Sequence<0>{}, Sequence<1>{}));
|
||||
|
||||
return matrix_padder.PadBDescriptor_N_K(b_grid_desc_nraw_kraw);
|
||||
}
|
||||
}
|
||||
|
||||
// assume E[M0, M1, M2, ..., N0, N1, N2...]
|
||||
static auto MakeEGridDescriptor_M_N(const std::vector<index_t>& e_ms_ns_lengths_vec,
|
||||
const std::vector<index_t>& e_ms_ns_strides_vec)
|
||||
{
|
||||
assert(e_ms_ns_lengths_vec.size() == NumDimM + NumDimN &&
|
||||
e_ms_ns_strides_vec.size() == NumDimM + NumDimN);
|
||||
|
||||
const auto to_tuple = [&](auto& vec, auto num) {
|
||||
return generate_tuple([&](auto i) { return vec[i]; }, num);
|
||||
};
|
||||
|
||||
const auto e_ms_ns_lengths = to_tuple(e_ms_ns_lengths_vec, Number<NumDimM + NumDimN>{});
|
||||
const auto e_ms_ns_strides = to_tuple(e_ms_ns_strides_vec, Number<NumDimM + NumDimN>{});
|
||||
|
||||
// dimension Ids for M0, M1, ...
|
||||
constexpr auto mDimIds = typename arithmetic_sequence_gen<0, NumDimM, 1>::type{};
|
||||
|
||||
// dimension Ids for N0, N1, ...
|
||||
constexpr auto nDimIds =
|
||||
typename arithmetic_sequence_gen<NumDimM, NumDimM + NumDimN, 1>::type{};
|
||||
|
||||
// lengths for M0, M1, ...
|
||||
const auto mLengths = get_container_subset(e_ms_ns_lengths, mDimIds);
|
||||
|
||||
// lengths for K0, K1, ...
|
||||
const auto nLengths = get_container_subset(e_ms_ns_lengths, nDimIds);
|
||||
|
||||
if constexpr(DESpec == TensorSpecialization::Packed)
|
||||
{
|
||||
auto M = container_reduce(mLengths, math::multiplies{}, Number<1>{});
|
||||
auto N = container_reduce(nLengths, math::multiplies{}, Number<1>{});
|
||||
const auto e_grid_desc_mraw_nraw = make_naive_tensor_descriptor(
|
||||
make_tuple(M, N),
|
||||
make_tuple(e_ms_ns_strides[Number<NumDimM - 1>{}],
|
||||
e_ms_ns_strides[Number<NumDimM + NumDimN - 1>{}]));
|
||||
return matrix_padder.PadCDescriptor_M_N(e_grid_desc_mraw_nraw);
|
||||
}
|
||||
else
|
||||
{
|
||||
// naive tensor E[M0, M1, M2, ..., N0, N1, N2...]
|
||||
const auto e_grid_desc_ms_ns =
|
||||
make_naive_tensor_descriptor(e_ms_ns_lengths, e_ms_ns_strides);
|
||||
|
||||
// transformed tensor E[MRaw = M0 * M1 * M2 * ... , NRaw = N0 * N1 * N2 * ...]
|
||||
const auto e_grid_desc_mraw_nraw = transform_tensor_descriptor(
|
||||
e_grid_desc_ms_ns,
|
||||
make_tuple(make_merge_transform(mLengths), make_merge_transform(nLengths)),
|
||||
make_tuple(mDimIds, nDimIds),
|
||||
make_tuple(Sequence<0>{}, Sequence<1>{}));
|
||||
|
||||
return matrix_padder.PadCDescriptor_M_N(e_grid_desc_mraw_nraw);
|
||||
}
|
||||
}
|
||||
|
||||
static auto MakeDsGridDescriptor_M_N(
|
||||
const std::array<std::vector<index_t>, NumDTensor>& ds_ms_ns_lengths_vec,
|
||||
const std::array<std::vector<index_t>, NumDTensor>& ds_ms_ns_strides_vec)
|
||||
{
|
||||
return generate_tuple(
|
||||
[&](auto i) {
|
||||
return DeviceOp::MakeEGridDescriptor_M_N(ds_ms_ns_lengths_vec[i],
|
||||
ds_ms_ns_strides_vec[i]);
|
||||
},
|
||||
Number<NumDTensor>{});
|
||||
}
|
||||
|
||||
using AGridDesc_M_K = decltype(MakeAGridDescriptor_M_K({}, {}));
|
||||
using BGridDesc_N_K = decltype(MakeBGridDescriptor_N_K({}, {}));
|
||||
using DsGridDesc_M_N = remove_cvref_t<decltype(MakeDsGridDescriptor_M_N({{}}, {{}}))>;
|
||||
using EGridDesc_M_N = decltype(MakeEGridDescriptor_M_N({}, {}));
|
||||
|
||||
// GridwiseGemm
|
||||
using GridwiseGemm = GridwiseGemmMultipleD_xdl_cshuffle<
|
||||
ADataType, // TODO: distinguish A/B datatype
|
||||
AccDataType,
|
||||
CShuffleDataType,
|
||||
DsDataType,
|
||||
EDataType,
|
||||
AElementwiseOperation,
|
||||
BElementwiseOperation,
|
||||
CDEElementwiseOperation,
|
||||
InMemoryDataOperationEnum::Set,
|
||||
AGridDesc_M_K,
|
||||
BGridDesc_N_K,
|
||||
DsGridDesc_M_N,
|
||||
EGridDesc_M_N,
|
||||
NumGemmKPrefetchStage,
|
||||
BlockSize,
|
||||
MPerBlock,
|
||||
NPerBlock,
|
||||
KPerBlock,
|
||||
AK1,
|
||||
BK1,
|
||||
MPerXDL,
|
||||
NPerXDL,
|
||||
MXdlPerWave,
|
||||
NXdlPerWave,
|
||||
ABlockTransferThreadClusterLengths_AK0_M_AK1,
|
||||
ABlockTransferThreadClusterArrangeOrder,
|
||||
ABlockTransferSrcAccessOrder,
|
||||
ABlockTransferSrcVectorDim,
|
||||
ABlockTransferSrcScalarPerVector,
|
||||
ABlockTransferDstScalarPerVector_AK1,
|
||||
false,
|
||||
ABlockLdsExtraM,
|
||||
BBlockTransferThreadClusterLengths_BK0_N_BK1,
|
||||
BBlockTransferThreadClusterArrangeOrder,
|
||||
BBlockTransferSrcAccessOrder,
|
||||
BBlockTransferSrcVectorDim,
|
||||
BBlockTransferSrcScalarPerVector,
|
||||
BBlockTransferDstScalarPerVector_BK1,
|
||||
false,
|
||||
BBlockLdsExtraN,
|
||||
CShuffleMXdlPerWavePerShuffle,
|
||||
CShuffleNXdlPerWavePerShuffle,
|
||||
CDEBlockTransferClusterLengths_MBlock_MPerBlock_NBlock_NPerBlock,
|
||||
CDEBlockTransferScalarPerVector_NPerBlock,
|
||||
LoopSched>;
|
||||
|
||||
using AGridDesc_AK0_M_AK1 = remove_cvref_t<decltype(
|
||||
GridwiseGemm::MakeDefaultAGridDescriptor_AK0_M_AK1(AGridDesc_M_K{}))>;
|
||||
using BGridDesc_BK0_N_BK1 = remove_cvref_t<decltype(
|
||||
GridwiseGemm::MakeDefaultBGridDescriptor_BK0_N_BK1(BGridDesc_N_K{}))>;
|
||||
|
||||
struct GroupedContractionBlock2ETileMap
|
||||
{
|
||||
static_assert(
|
||||
std::is_same<decltype(GridwiseGemm::MakeDefaultBlock2ETileMap(EGridDesc_M_N{})),
|
||||
typename GridwiseGemm::DefaultBlock2ETileMap>::value,
|
||||
"Wrong! Should be the same type name");
|
||||
|
||||
GroupedContractionBlock2ETileMap(const EGridDesc_M_N& e_grid_desc_m_n,
|
||||
ck::index_t BlockStart)
|
||||
{
|
||||
default_block_2_etile_map_ = GridwiseGemm::MakeDefaultBlock2ETileMap(e_grid_desc_m_n);
|
||||
block_start_ = BlockStart;
|
||||
}
|
||||
|
||||
template <typename TopIdx>
|
||||
__host__ __device__ constexpr auto CalculateBottomIndex(const TopIdx& idx_top) const
|
||||
{
|
||||
return default_block_2_etile_map_.CalculateBottomIndex(
|
||||
make_multi_index(idx_top[I0] - block_start_));
|
||||
}
|
||||
|
||||
// it's actually E-Tile
|
||||
template <typename CTileIdx, typename CTileDim>
|
||||
__host__ __device__ bool ValidCTileIndex(const CTileIdx& c_tile_idx,
|
||||
const CTileDim& c_tile_dim) const
|
||||
{
|
||||
return default_block_2_etile_map_.ValidCTileIndex(c_tile_idx, c_tile_dim);
|
||||
}
|
||||
|
||||
__host__ bool CheckValidity(const EGridDesc_M_N& e_grid_desc_m_n) const
|
||||
{
|
||||
return default_block_2_etile_map_.CheckValidity(e_grid_desc_m_n);
|
||||
}
|
||||
|
||||
typename GridwiseGemm::DefaultBlock2ETileMap default_block_2_etile_map_;
|
||||
ck::index_t block_start_;
|
||||
};
|
||||
|
||||
struct ContractionMultiDKernelArg
|
||||
{
|
||||
// pointers
|
||||
const ADataType* p_a_grid_;
|
||||
const BDataType* p_b_grid_;
|
||||
typename GridwiseGemm::DsGridPointer p_ds_grid_;
|
||||
EDataType* p_e_grid_;
|
||||
|
||||
// tensor descriptors for block/thread-wise copy
|
||||
AGridDesc_AK0_M_AK1 a_grid_desc_ak0_m_ak1_;
|
||||
BGridDesc_BK0_N_BK1 b_grid_desc_bk0_n_bk1_;
|
||||
typename GridwiseGemm::DsGridDescriptor_MBlock_MPerBlock_NBlock_NPerBlock
|
||||
ds_grid_desc_mblock_mperblock_nblock_nperblock_;
|
||||
typename GridwiseGemm::EGridDescriptor_MBlock_MPerBlock_NBlock_NPerBlock
|
||||
e_grid_desc_mblock_mperblock_nblock_nperblock_;
|
||||
|
||||
// lock-to-e-tile map
|
||||
GroupedContractionBlock2ETileMap block_2_etile_map_;
|
||||
|
||||
ck::index_t block_start_, block_end_;
|
||||
};
|
||||
|
||||
struct ContractionMultiDDeviceArg
|
||||
{
|
||||
// tensor descriptors for problem definiton
|
||||
AGridDesc_M_K a_grid_desc_m_k_;
|
||||
BGridDesc_N_K b_grid_desc_n_k_;
|
||||
DsGridDesc_M_N ds_grid_desc_m_n_;
|
||||
EGridDesc_M_N e_grid_desc_m_n_;
|
||||
|
||||
// Strides for the last M/N/K dimensions of A/B/Ds/E
|
||||
// for sanity check of vector load/store
|
||||
index_t a_mz_stride_;
|
||||
index_t a_kz_stride_;
|
||||
index_t b_nz_stride_;
|
||||
index_t b_kz_stride_;
|
||||
std::array<index_t, NumDTensor> ds_nz_stride_;
|
||||
// index_t e_mz_stride_;
|
||||
index_t e_nz_stride_;
|
||||
};
|
||||
|
||||
// Argument
|
||||
struct Argument : public BaseArgument
|
||||
{
|
||||
Argument(std::vector<const void*> p_a_vec,
|
||||
std::vector<const void*> p_b_vec,
|
||||
std::vector<std::array<const void*, NumDTensor>> p_ds_vec,
|
||||
std::vector<void*> p_e_vec,
|
||||
std::vector<ContractionDesc<NumDTensor>> contraction_descs,
|
||||
AElementwiseOperation a_element_op,
|
||||
BElementwiseOperation b_element_op,
|
||||
CDEElementwiseOperation cde_element_op)
|
||||
: a_element_op_{a_element_op},
|
||||
b_element_op_{b_element_op},
|
||||
cde_element_op_{cde_element_op}
|
||||
{
|
||||
group_count_ = contraction_descs.size();
|
||||
|
||||
if(!(group_count_ == p_a_vec.size() && group_count_ == p_b_vec.size() &&
|
||||
group_count_ == p_e_vec.size()))
|
||||
{
|
||||
throw std::runtime_error("wrong! group_count_ != a/b/e_vec.size");
|
||||
}
|
||||
|
||||
contraction_multi_d_kernel_args_.reserve(group_count_);
|
||||
|
||||
grid_size_ = 0;
|
||||
|
||||
for(std::size_t i = 0; i < group_count_; i++)
|
||||
{
|
||||
const auto p_a_grid = static_cast<const ADataType*>(p_a_vec[i]);
|
||||
const auto p_b_grid = static_cast<const BDataType*>(p_b_vec[i]);
|
||||
const auto p_e_grid = static_cast<EDataType*>(p_e_vec[i]);
|
||||
|
||||
const auto a_grid_desc_m_k = DeviceOp::MakeAGridDescriptor_M_K(
|
||||
contraction_descs[i].a_ms_ks_lengths, contraction_descs[i].a_ms_ks_strides);
|
||||
const auto b_grid_desc_n_k = DeviceOp::MakeBGridDescriptor_N_K(
|
||||
contraction_descs[i].b_ns_ks_lengths, contraction_descs[i].b_ns_ks_strides);
|
||||
|
||||
DsGridDesc_M_N ds_grid_desc_m_n;
|
||||
typename GridwiseGemm::DsGridPointer p_ds_grid;
|
||||
|
||||
// populate pointer, batch stride, desc for Ds
|
||||
static_for<0, NumDTensor, 1>{}([&](auto j) {
|
||||
using DDataType = remove_cvref_t<tuple_element_t<j.value, DsDataType>>;
|
||||
|
||||
// D pointer
|
||||
p_ds_grid(j) = static_cast<const DDataType*>(p_ds_vec[i][j]);
|
||||
|
||||
// D desc
|
||||
ds_grid_desc_m_n(j) =
|
||||
DeviceOp::MakeEGridDescriptor_M_N(contraction_descs[i].ds_ms_ns_lengths[j],
|
||||
contraction_descs[i].ds_ms_ns_strides[j]);
|
||||
});
|
||||
|
||||
const auto e_grid_desc_m_n = DeviceOp::MakeEGridDescriptor_M_N(
|
||||
contraction_descs[i].e_ms_ns_lengths, contraction_descs[i].e_ms_ns_strides);
|
||||
|
||||
const auto a_grid_desc_ak0_m_ak1 =
|
||||
GridwiseGemm::MakeDefaultAGridDescriptor_AK0_M_AK1(a_grid_desc_m_k);
|
||||
const auto b_grid_desc_bk0_n_bk1 =
|
||||
GridwiseGemm::MakeDefaultBGridDescriptor_BK0_N_BK1(b_grid_desc_n_k);
|
||||
|
||||
const auto ds_grid_desc_mblock_mperblock_nblock_nperblock =
|
||||
GridwiseGemm::MakeDsGridDescriptor_MBlock_MPerBlock_NBlock_NPerBlock(
|
||||
ds_grid_desc_m_n);
|
||||
const auto e_grid_desc_mblock_mperblock_nblock_nperblock =
|
||||
GridwiseGemm::MakeEGridDescriptor_MBlock_MPerBlock_NBlock_NPerBlock(
|
||||
e_grid_desc_m_n);
|
||||
|
||||
const index_t grid_size_grp =
|
||||
GridwiseGemm::MakeDefaultBlock2ETileMap(e_grid_desc_m_n)
|
||||
.CalculateGridSize(e_grid_desc_m_n);
|
||||
|
||||
const index_t BlockStart = grid_size_;
|
||||
const index_t BlockEnd = grid_size_ + grid_size_grp;
|
||||
|
||||
grid_size_ += grid_size_grp;
|
||||
|
||||
const auto block_2_etile_map =
|
||||
GroupedContractionBlock2ETileMap(e_grid_desc_m_n, BlockStart);
|
||||
|
||||
// for sanity check of vector memory access
|
||||
const index_t a_mz_stride = contraction_descs[i].a_ms_ks_strides[NumDimM - 1];
|
||||
const index_t a_kz_stride =
|
||||
contraction_descs[i].a_ms_ks_strides[NumDimM + NumDimK - 1];
|
||||
|
||||
const index_t b_nz_stride = contraction_descs[i].b_ns_ks_strides[NumDimN - 1];
|
||||
const index_t b_kz_stride =
|
||||
contraction_descs[i].b_ns_ks_strides[NumDimN + NumDimK - 1];
|
||||
|
||||
std::array<index_t, NumDTensor> ds_nz_stride;
|
||||
for(index_t j = 0; j < NumDTensor; ++j)
|
||||
{
|
||||
ds_nz_stride[j] =
|
||||
contraction_descs[i].ds_ms_ns_strides[j][NumDimM + NumDimN - 1];
|
||||
}
|
||||
|
||||
const index_t e_nz_stride =
|
||||
contraction_descs[i].e_ms_ns_strides[NumDimM + NumDimN - 1];
|
||||
|
||||
if(GridwiseGemm::CheckValidity(a_grid_desc_m_k,
|
||||
b_grid_desc_n_k,
|
||||
ds_grid_desc_m_n,
|
||||
e_grid_desc_m_n,
|
||||
block_2_etile_map))
|
||||
{
|
||||
contraction_multi_d_kernel_args_.push_back(
|
||||
{p_a_grid,
|
||||
p_b_grid,
|
||||
p_ds_grid,
|
||||
p_e_grid,
|
||||
a_grid_desc_ak0_m_ak1,
|
||||
b_grid_desc_bk0_n_bk1,
|
||||
ds_grid_desc_mblock_mperblock_nblock_nperblock,
|
||||
e_grid_desc_mblock_mperblock_nblock_nperblock,
|
||||
block_2_etile_map,
|
||||
BlockStart,
|
||||
BlockEnd});
|
||||
|
||||
contraction_multi_d_device_args_.push_back({a_grid_desc_m_k,
|
||||
b_grid_desc_n_k,
|
||||
ds_grid_desc_m_n,
|
||||
e_grid_desc_m_n,
|
||||
a_mz_stride,
|
||||
a_kz_stride,
|
||||
b_nz_stride,
|
||||
b_kz_stride,
|
||||
ds_nz_stride,
|
||||
e_nz_stride});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
std::vector<ContractionMultiDKernelArg> contraction_multi_d_kernel_args_;
|
||||
std::vector<ContractionMultiDDeviceArg> contraction_multi_d_device_args_;
|
||||
|
||||
std::size_t group_count_;
|
||||
index_t grid_size_;
|
||||
|
||||
// element-wise op
|
||||
AElementwiseOperation a_element_op_;
|
||||
BElementwiseOperation b_element_op_;
|
||||
CDEElementwiseOperation cde_element_op_;
|
||||
};
|
||||
|
||||
// Invoker
|
||||
struct Invoker : public BaseInvoker
|
||||
{
|
||||
using Argument = DeviceOp::Argument;
|
||||
|
||||
float Run(const Argument& arg, const StreamConfig& stream_config = StreamConfig{})
|
||||
{
|
||||
bool has_main_k_block_loop = true;
|
||||
|
||||
for(std::size_t i = 0; i < arg.group_count_; i++)
|
||||
{
|
||||
const auto K =
|
||||
arg.contraction_multi_d_kernel_args_[i].a_grid_desc_ak0_m_ak1_.GetLength(I0) *
|
||||
arg.contraction_multi_d_kernel_args_[i].a_grid_desc_ak0_m_ak1_.GetLength(I2);
|
||||
|
||||
if(GridwiseGemm::CalculateHasMainKBlockLoop(K) != has_main_k_block_loop)
|
||||
{
|
||||
throw std::runtime_error("wrong! not all gemm has_main_k_block_loop");
|
||||
}
|
||||
}
|
||||
|
||||
hipGetErrorString(hipMemcpy(arg.p_workspace_,
|
||||
arg.contraction_multi_d_kernel_args_.data(),
|
||||
arg.contraction_multi_d_kernel_args_.size() *
|
||||
sizeof(ContractionMultiDKernelArg),
|
||||
hipMemcpyHostToDevice));
|
||||
|
||||
float ave_time = 0;
|
||||
|
||||
auto launch_kernel = [&](auto has_main_k_block_loop_) {
|
||||
const auto kernel =
|
||||
kernel_grouped_contraction_multiple_d_xdl_cshuffle<GridwiseGemm,
|
||||
ContractionMultiDKernelArg,
|
||||
AElementwiseOperation,
|
||||
BElementwiseOperation,
|
||||
CDEElementwiseOperation,
|
||||
has_main_k_block_loop_>;
|
||||
|
||||
return launch_and_time_kernel(
|
||||
stream_config,
|
||||
kernel,
|
||||
dim3(arg.grid_size_),
|
||||
dim3(BlockSize),
|
||||
0,
|
||||
cast_pointer_to_constant_address_space(arg.p_workspace_),
|
||||
arg.group_count_,
|
||||
arg.a_element_op_,
|
||||
arg.b_element_op_,
|
||||
arg.cde_element_op_);
|
||||
};
|
||||
|
||||
if(has_main_k_block_loop)
|
||||
{
|
||||
ave_time = launch_kernel(integral_constant<bool, true>{});
|
||||
}
|
||||
else
|
||||
{
|
||||
ave_time = launch_kernel(integral_constant<bool, false>{});
|
||||
}
|
||||
|
||||
return ave_time;
|
||||
}
|
||||
|
||||
// polymorphic
|
||||
float Run(const BaseArgument* p_arg,
|
||||
const StreamConfig& stream_config = StreamConfig{}) override
|
||||
{
|
||||
return Run(*dynamic_cast<const Argument*>(p_arg), stream_config);
|
||||
}
|
||||
};
|
||||
|
||||
static bool IsSupportedArgument(const Argument& arg)
|
||||
{
|
||||
if(!(ck::get_device_name() == "gfx908" || ck::get_device_name() == "gfx90a"))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
for(std::size_t i = 0; i < arg.group_count_; i++)
|
||||
{
|
||||
const auto a_grid_desc_m_k_ = arg.contraction_multi_d_device_args_[i].a_grid_desc_m_k_;
|
||||
const auto b_grid_desc_n_k_ = arg.contraction_multi_d_device_args_[i].b_grid_desc_n_k_;
|
||||
const auto ds_grid_desc_m_n_ =
|
||||
arg.contraction_multi_d_device_args_[i].ds_grid_desc_m_n_;
|
||||
const auto e_grid_desc_m_n_ = arg.contraction_multi_d_device_args_[i].e_grid_desc_m_n_;
|
||||
const auto a_grid_desc_ak0_m_ak1_ =
|
||||
arg.contraction_multi_d_kernel_args_[i].a_grid_desc_ak0_m_ak1_;
|
||||
const auto b_grid_desc_bk0_n_bk1_ =
|
||||
arg.contraction_multi_d_kernel_args_[i].b_grid_desc_bk0_n_bk1_;
|
||||
const auto ds_grid_desc_mblock_mperblock_nblock_nperblock_ =
|
||||
arg.contraction_multi_d_kernel_args_[i]
|
||||
.ds_grid_desc_mblock_mperblock_nblock_nperblock_;
|
||||
const auto e_grid_desc_mblock_mperblock_nblock_nperblock_ =
|
||||
arg.contraction_multi_d_kernel_args_[i]
|
||||
.e_grid_desc_mblock_mperblock_nblock_nperblock_;
|
||||
|
||||
const auto block_2_etile_map_ =
|
||||
arg.contraction_multi_d_kernel_args_[i].block_2_etile_map_;
|
||||
|
||||
const auto a_mz_stride_ = arg.contraction_multi_d_device_args_[i].a_mz_stride_;
|
||||
const auto a_kz_stride_ = arg.contraction_multi_d_device_args_[i].a_kz_stride_;
|
||||
const auto b_nz_stride_ = arg.contraction_multi_d_device_args_[i].b_nz_stride_;
|
||||
const auto b_kz_stride_ = arg.contraction_multi_d_device_args_[i].b_kz_stride_;
|
||||
const auto ds_nz_stride_ = arg.contraction_multi_d_device_args_[i].ds_nz_stride_;
|
||||
const auto e_nz_stride_ = arg.contraction_multi_d_device_args_[i].e_nz_stride_;
|
||||
|
||||
if(!GridwiseGemm::CheckValidity(a_grid_desc_m_k_,
|
||||
b_grid_desc_n_k_,
|
||||
ds_grid_desc_m_n_,
|
||||
e_grid_desc_m_n_,
|
||||
block_2_etile_map_))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
// check vector access
|
||||
static_assert((ABlockTransferSrcVectorDim == 1 || ABlockTransferSrcVectorDim == 2) &&
|
||||
(BBlockTransferSrcVectorDim == 1 || BBlockTransferSrcVectorDim == 2),
|
||||
"wrong!");
|
||||
|
||||
// vector memory access of A: could be on M or AK1 dimension
|
||||
if constexpr(ABlockTransferSrcVectorDim == 1)
|
||||
{
|
||||
if(!(a_mz_stride_ == 1 &&
|
||||
a_grid_desc_ak0_m_ak1_.GetLength(I1) % ABlockTransferSrcScalarPerVector == 0))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(!(a_kz_stride_ == 1 &&
|
||||
a_grid_desc_ak0_m_ak1_.GetLength(I2) % ABlockTransferSrcScalarPerVector == 0))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
// vector memory access of B: could be on N or BK1 dimension
|
||||
if constexpr(BBlockTransferSrcVectorDim == 1)
|
||||
{
|
||||
if(!(b_nz_stride_ == 1 &&
|
||||
b_grid_desc_bk0_n_bk1_.GetLength(I1) % BBlockTransferSrcScalarPerVector == 0))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(!(b_kz_stride_ == 1 &&
|
||||
b_grid_desc_bk0_n_bk1_.GetLength(I2) % BBlockTransferSrcScalarPerVector == 0))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
// vector memory access of Ds: always on NPerBlock dimension
|
||||
bool valid_d_access = true;
|
||||
|
||||
static_for<0, NumDTensor, 1>{}([&](auto j) {
|
||||
if(!(ds_nz_stride_[j] == 1 &&
|
||||
ds_grid_desc_mblock_mperblock_nblock_nperblock_[j].GetLength(I3) %
|
||||
CDEBlockTransferScalarPerVector_NPerBlock ==
|
||||
0))
|
||||
{
|
||||
valid_d_access = false;
|
||||
}
|
||||
});
|
||||
|
||||
if(valid_d_access == false)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
// vector memory access of E: always on NPerBlock dimension
|
||||
if(!(e_nz_stride_ == 1 && e_grid_desc_mblock_mperblock_nblock_nperblock_.GetLength(I3) %
|
||||
CDEBlockTransferScalarPerVector_NPerBlock ==
|
||||
0))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
// polymorphic
|
||||
bool IsSupportedArgument(const BaseArgument* p_arg) override
|
||||
{
|
||||
return IsSupportedArgument(*dynamic_cast<const Argument*>(p_arg));
|
||||
}
|
||||
|
||||
static auto MakeArgument(std::vector<const void*> p_a_vec,
|
||||
std::vector<const void*> p_b_vec,
|
||||
std::vector<std::array<const void*, NumDTensor>> p_ds_vec,
|
||||
std::vector<void*> p_e_vec,
|
||||
std::vector<ContractionDesc<NumDTensor>> contraction_descs,
|
||||
AElementwiseOperation a_element_op,
|
||||
BElementwiseOperation b_element_op,
|
||||
CDEElementwiseOperation cde_element_op)
|
||||
{
|
||||
return Argument{p_a_vec,
|
||||
p_b_vec,
|
||||
p_ds_vec,
|
||||
p_e_vec,
|
||||
contraction_descs,
|
||||
a_element_op,
|
||||
b_element_op,
|
||||
cde_element_op};
|
||||
}
|
||||
|
||||
static auto MakeInvoker() { return Invoker{}; }
|
||||
|
||||
// polymorphic
|
||||
std::unique_ptr<BaseArgument>
|
||||
MakeArgumentPointer(std::vector<const void*> p_a_vec,
|
||||
std::vector<const void*> p_b_vec,
|
||||
std::vector<std::array<const void*, NumDTensor>> p_ds_vec,
|
||||
std::vector<void*> p_e_vec,
|
||||
std::vector<ContractionDesc<NumDTensor>> contraction_descs,
|
||||
AElementwiseOperation a_element_op,
|
||||
BElementwiseOperation b_element_op,
|
||||
CDEElementwiseOperation cde_element_op) override
|
||||
{
|
||||
return std::make_unique<Argument>(p_a_vec,
|
||||
p_b_vec,
|
||||
p_ds_vec,
|
||||
p_e_vec,
|
||||
contraction_descs,
|
||||
a_element_op,
|
||||
b_element_op,
|
||||
cde_element_op);
|
||||
}
|
||||
|
||||
// polymorphic
|
||||
std::unique_ptr<BaseInvoker> MakeInvokerPointer() override
|
||||
{
|
||||
return std::make_unique<Invoker>(Invoker{});
|
||||
}
|
||||
|
||||
// polymorphic
|
||||
std::string GetTypeString() const override
|
||||
{
|
||||
auto str = std::stringstream();
|
||||
|
||||
// clang-format off
|
||||
str << "DeviceGroupedContractionMultipleD_Xdl_CShuffle"
|
||||
<< "<"
|
||||
<< NumDimM << ", "
|
||||
<< NumDimN << ", "
|
||||
<< NumDimK << ", "
|
||||
<< BlockSize << ", "
|
||||
<< MPerBlock << ", "
|
||||
<< NPerBlock << ", "
|
||||
<< KPerBlock << ", "
|
||||
<< AK1 << ", "
|
||||
<< BK1 << ", "
|
||||
<< ABlockTransferSrcVectorDim << ", "
|
||||
<< BBlockTransferSrcVectorDim
|
||||
<< ">";
|
||||
// clang-format on
|
||||
|
||||
return str.str();
|
||||
}
|
||||
|
||||
size_t GetWorkSpaceSize(const BaseArgument* p_arg) const override
|
||||
{
|
||||
return dynamic_cast<const Argument*>(p_arg)->group_count_ *
|
||||
sizeof(ContractionMultiDKernelArg);
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace device
|
||||
} // namespace tensor_operation
|
||||
} // namespace ck
|
||||
@@ -0,0 +1,28 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
// Copyright (c) 2018-2022, Advanced Micro Devices, Inc. All rights reserved.
|
||||
|
||||
#pragma once
|
||||
|
||||
namespace ck {
|
||||
namespace tensor_operation {
|
||||
namespace device {
|
||||
|
||||
enum struct TensorSpecialization
|
||||
{
|
||||
Default,
|
||||
Packed
|
||||
};
|
||||
|
||||
inline std::string getTensorSpecializationString(const TensorSpecialization& s)
|
||||
{
|
||||
switch(s)
|
||||
{
|
||||
case TensorSpecialization::Default: return "Default";
|
||||
case TensorSpecialization::Packed: return "Packed";
|
||||
default: return "Unrecognized specialization!";
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace device
|
||||
} // namespace tensor_operation
|
||||
} // namespace ck
|
||||
Reference in New Issue
Block a user