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fixed vector load siz for fp4

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This commit is contained in:
Sami Remes
2026-01-16 12:04:34 -05:00
parent 16ca5cb532
commit f09e10936d
7 changed files with 66 additions and 50 deletions
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4
include/ck_tile/ops/gemm/kernel/universal_gemm_kernel.hpp
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@@ -673,8 +673,8 @@ struct UniversalGemmKernel
using AiLayout = remove_cvref_t<std::tuple_element_t<i.value, AsLayout>>;
using AiDataType = remove_cvref_t<std::tuple_element_t<i.value, AsDataType>>;
static_assert(GemmPipeline::GetVectorSizeA() == GemmPipeline::GetVectorSizeB(), "Vector size of A and B must be the same!");
static_assert(GemmPipeline::GetVectorSizeA() == 16, "Vector size of A must be 16!");
static_assert(GemmPipeline::GetVectorSizeB() == 16, "Vector size of B must be 16!");
static_assert(GemmPipeline::GetVectorSizeA() == 32, "Vector size of A must be 16!");
static_assert(GemmPipeline::GetVectorSizeB() == 32, "Vector size of B must be 16!");
if constexpr(std::is_same_v<AiLayout, tensor_layout::gemm::RowMajor>)
{
return make_naive_tensor_view<address_space_enum::global>(

6
include/ck_tile/ops/gemm/pipeline/gemm_universal_pipeline_ag_bg_cr_policy.hpp
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@@ -843,7 +843,7 @@ struct UniversalGemmBasePolicy
}
template <typename Problem>
CK_TILE_DEVICE static constexpr index_t GetSmemSizeA()
CK_TILE_HOST_DEVICE static constexpr index_t GetSmemSizeA()
{
using ADataType = remove_cvref_t<typename Problem::ADataType>;
constexpr auto a_lds_block_desc = Derived::template MakeALdsBlockDescriptor<Problem>();
@@ -853,7 +853,7 @@ struct UniversalGemmBasePolicy
}
template <typename Problem>
CK_TILE_DEVICE static constexpr index_t GetSmemSizeB()
CK_TILE_HOST_DEVICE static constexpr index_t GetSmemSizeB()
{
using BDataType =
std::conditional_t<std::is_same_v<typename Problem::BDataType, pk_fp4_raw_t>,
@@ -866,7 +866,7 @@ struct UniversalGemmBasePolicy
}
template <typename Problem>
CK_TILE_DEVICE static constexpr index_t GetSmemSize()
CK_TILE_HOST_DEVICE static constexpr index_t GetSmemSize()
{
constexpr index_t smem_size_a = GetSmemSizeA<Problem>();
constexpr index_t smem_size_b = GetSmemSizeB<Problem>();

4
include/ck_tile/ops/gemm_mx/pipeline/gemm_pipeline_ag_bg_cr_comp_async.hpp
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@@ -316,10 +316,10 @@ struct MXGemmPipelineAgBgCrCompAsync : public BaseMXGemmPipelineAgBgCrCompAsync<
number<BsLayout::size()>{});
/// Check tile window traits for vector size
using ATileDstr = remove_cvref_t<decltype(Policy::template MakeADramTileDistribution<Problem>())>;
// using ATileDstr = remove_cvref_t<decltype(Policy::template MakeADramTileDistribution<Problem>())>;
// static_assert(ATileDstr::LargestVec >= 16, "wrong! not implemented vector size");
// static_assert(ATileDstr::X1 >= 16, "wrong! not implemented vector size");
using BTileDstr = remove_cvref_t<decltype(Policy::template MakeBDramTileDistribution<Problem>())>;
// using BTileDstr = remove_cvref_t<decltype(Policy::template MakeBDramTileDistribution<Problem>())>;
// static_assert(BTileDstr::LargestVec >= 16, "wrong! not implemented vector size");
// static_assert(BTileDstr::X1 >= 16, "wrong! not implemented vector size");
using ATileType = remove_cvref_t<decltype(a_tile_windows[number<0>{}])>;

20
include/ck_tile/ops/gemm_mx/pipeline/gemm_pipeline_ag_bg_cr_comp_async_default_policy.hpp
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@@ -39,7 +39,15 @@ struct MXGemmPipelineAgBgCrCompAsyncDefaultPolicy
// constexpr index_t vector_size_for_16_bytes = 16 / sizeof(ADataType);
// return vector_size_for_16_bytes;
return 16;
static_assert(std::is_same_v<ADataType, pk_fp4_t>, "ADataType must be pk_fp4_t or pk_fp4_raw_t");
if constexpr(std::is_same_v<ADataType, pk_fp4_t> || std::is_same_v<ADataType, pk_fp4_raw_t>)
{
return 32;
}
else
{
return 16;
}
}
template <typename Problem, bool IsWave32Host = false>
@@ -55,7 +63,15 @@ struct MXGemmPipelineAgBgCrCompAsyncDefaultPolicy
// constexpr index_t vector_size_for_16_bytes = 16 / sizeof(BDataType);
// return vector_size_for_16_bytes;
return 16;
static_assert(std::is_same_v<BDataType, pk_fp4_t>, "BDataType must be pk_fp4_t or pk_fp4_raw_t");
if constexpr(std::is_same_v<BDataType, pk_fp4_t> || std::is_same_v<BDataType, pk_fp4_raw_t>)
{
return 32;
}
else
{
return 16;
}
}
// Override DRAM tile distributions to use the constrained vector sizes