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This reverts commit 2cbbf5dcb3.
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@@ -240,7 +240,7 @@ struct FusedMoeGemmKernel
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if constexpr(UseUK)
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{
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__shared__ CK_TILE_LDS_ADDR char smem[GetSmemSize()];
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IndexDataType num_sorted_tiles = amd_wave_read_first_lane(
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IndexDataType num_sorted_tiles = __builtin_amdgcn_readfirstlane(
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*reinterpret_cast<const IndexDataType*>(kargs.num_sorted_tiles_ptr));
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num_sorted_tiles = num_sorted_tiles / BlockShape::Block_M0;
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@@ -261,7 +261,7 @@ struct FusedMoeGemmKernel
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{
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// allocate LDS
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// __shared__ char smem_ptr[GetSmemSize()];
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IndexDataType num_sorted_tiles = amd_wave_read_first_lane(
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IndexDataType num_sorted_tiles = __builtin_amdgcn_readfirstlane(
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*reinterpret_cast<const IndexDataType*>(kargs.num_sorted_tiles_ptr));
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constexpr index_t hidden_radio_0 = IsGateOnly ? 1 : 2;
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@@ -283,14 +283,14 @@ struct FusedMoeGemmKernel
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return;
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const IndexDataType expert_id =
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amd_wave_read_first_lane(reinterpret_cast<const IndexDataType*>(
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__builtin_amdgcn_readfirstlane(reinterpret_cast<const IndexDataType*>(
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kargs.sorted_expert_ids_ptr)[sorted_tile_id]);
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// index along intermediate_size
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// index_t hidden_idx = __builtin_amdgcn_readfirstlane(intermediate_tile_id *
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// BlockShape::Block_N0);
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index_t interm_idx_nr =
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amd_wave_read_first_lane(intermediate_tile_id * BlockShape::Block_Nr0);
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__builtin_amdgcn_readfirstlane(intermediate_tile_id * BlockShape::Block_Nr0);
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const auto a_coord = Pipeline::GetACoord(); // 2d thread offset, [i_row, i_col]
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const auto sorted_token_id =
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@@ -756,7 +756,7 @@ struct MoeSortingKernel
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void* smem) const
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{
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const index_t tid = static_cast<index_t>(threadIdx.x);
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const index_t wid = amd_wave_read_first_lane(tid / get_warp_size());
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const index_t wid = __builtin_amdgcn_readfirstlane(tid / get_warp_size());
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const index_t lid = __lane_id();
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constexpr index_t block_size = 256; // blockDim.x;
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const index_t sub_tokens = smem_rows - 2; // sub_tokens_mdiv.divisor;
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