76 Commits

Author	SHA1	Message	Date
Chao Liu	8f5f64960e	backward data (#7) ... * enabled atomic add in tensor copy * added gridwise GEMM * added backward data conv using GEMM + atomic * added backward data conv using GEMM, no atomic	2019-12-03 01:16:12 -06:00
Chao Liu	562e1e2767	MIOpen integration: recent bug fixes from MIOpen (#5)	2019-11-04 16:51:12 -06:00
Chao Liu	52c3fe05be	Refactor for MIOpen integration (#4) ... Refactor, so can bring multi-index transformation and padding support into MIOpen	2019-10-11 11:37:31 -05:00
Chao Liu	cf21818455	enable type conversion in blockwise copy v2 and threadwise copy v2r1	2019-09-30 15:11:05 -05:00
Chao Liu	012d3a071b	tweaking	2019-09-27 16:38:11 -05:00
Chao Liu	14315b72f3	tweaking	2019-09-27 15:24:27 -05:00
Chao Liu	ebe38f3d48	debugging	2019-09-27 11:31:01 -05:00
Chao Liu	9b280cc50d	remove dead code	2019-09-27 02:00:59 -05:00
Chao Liu	00089cd6e5	clean up	2019-09-26 21:39:28 -05:00
Chao Liu	b12bbceebc	clean up	2019-09-26 14:59:19 -05:00
Chao Liu	51a9fa1dbd	removing dependency on old tensor descriptor	2019-09-26 11:49:05 -05:00
Chao Liu	39d92e7dfd	removing old implementation of tensor descriptor	2019-09-25 22:24:06 -05:00
Chao Liu	012b525377	clean up	2019-09-25 03:28:53 -05:00
Chao Liu	545d930568	refactor	2019-09-24 18:06:05 -05:00
Chao Liu	51884fc214	WIP: explicitly separate offset component into compile-time, block-invariant and per-thread components	2019-09-21 22:53:03 -05:00
Chao Liu	bf7e7d62a8	refactor	2019-09-19 23:44:23 -05:00
Chao Liu	94bb1b4835	refactor	2019-09-18 16:08:24 -05:00
Chao Liu	86cc678f18	add global_load and buffer_load inline asm	2019-09-18 15:41:55 -05:00
Chao Liu	5b7a18c506	experimenting global and buffer load/store	2019-09-18 02:05:42 -05:00
Chao Liu	c7a6545ec4	experimenting global and buffer load/store	2019-09-18 01:37:28 -05:00
Chao Liu	9f46cdf5fa	experimenting global and buffer load/store	2019-09-18 00:15:57 -05:00
Chao Liu	f58bf38445	enable hip compiler flag: -amdgpu-enable-global-sgpr-addr	2019-09-17 17:34:39 -05:00
Chao Liu	126cae0c9b	bug fix	2019-09-17 15:02:12 -05:00
Chao Liu	f7be86b9e4	refactor	2019-09-16 22:47:55 -05:00
Chao Liu	d707993933	bug fix	2019-09-15 20:57:07 -05:00
Chao Liu	69fea593ec	amd build	2019-09-15 17:55:46 -05:00
Chao Liu	940949d9d5	add lds doble buffer to nchw padded v4r1 and v4r4	2019-09-15 16:59:54 -05:00
Chao Liu	bf97542846	add lds doble buffer to nchw padded v4r1 and v4r4	2019-09-15 16:58:16 -05:00
Chao Liu	2c93b3057d	initial implementation for nchw v4r4 padding	2019-09-15 16:31:54 -05:00
Chao Liu	53094f7fae	clean up	2019-09-15 12:13:58 -05:00
Chao Liu	d4878d99f9	initial padding support for nchw	2019-09-13 23:30:48 -05:00
Chao Liu	bd7a230006	clean up	2019-09-12 14:55:46 -05:00
Chao Liu	1f70524471	padding for chwn is functional	2019-09-12 01:12:08 -05:00
Chao Liu	724e984bff	enabling padding for chwn format	2019-09-11 01:13:13 -05:00
Chao Liu	ca42e9101d	adding merge transform	2019-09-10 01:53:49 -05:00
Chao Liu	7a7fe16086	more utility code	2019-09-09 00:29:33 -05:00
Chao Liu	625838def0	added tuple	2019-09-06 18:07:56 -05:00
Chao Liu	cb6475c77d	clean	2019-08-23 09:59:23 -05:00
Chao Liu	238d58c2f5	adding tensor_view	2019-08-20 17:29:54 -05:00
Chao Liu	86ceded98b	Merge remote-tracking branch 'origin/master' into add_padding	2019-08-15 13:48:45 -05:00
Chao Liu	0979fb4af9	clean up	2019-08-15 13:21:51 -05:00
Chao Liu	4fb81e008c	adding padding to implicit gemm v1r3	2019-08-14 10:55:34 -05:00
Chao Liu	740149fcf1	clean up	2019-08-13 17:26:00 -05:00
Chao Liu	40836ab926	add back some code	2019-08-13 12:21:38 -05:00
Chao Liu	8bdaba51f8	clean up	2019-08-13 00:37:23 -05:00
Chao Liu	1c4ef23cff	cleaning up	2019-08-09 22:48:28 -05:00
Chao Liu	4908fe3fdc	tweak on amd	2019-08-08 12:14:06 -05:00
Chao Liu	701b7341f0	clean up	2019-08-07 19:25:54 -05:00
Chao Liu	bc9ea646f8	use ford/for instead of static_ford/static_for in threadwise copy, somehow register spill is greatly reduced on AMD	2019-08-07 19:09:13 -05:00
Chao Liu	1b3c2e4035	reworked ThreadwiseGenericTensorSliceCopy_v1	2019-08-07 00:52:13 -05:00