3 Commits

Author	SHA1	Message	Date
ltqin	880fbee957	NHWC conv 2d: fwd bfp16/int8, Device level tuning and host API (#73) ... * add fwd bf16 conv * change tunning parametor * add int8 for conv fwd * remove comments * change tunning parametor for int8 * change init int8 example * add test for conv2d fwd * change device operation file pos because merge develop * fwd int8 use reference * test_conv_fwd use reference * add braket for if statement * rename fwd example name * remove StaticBufferOfVectorTypeV2 * tweak example Co-authored-by: ltqin <letaoqin@amd.com> Co-authored-by: Chao Liu <chao.liu2@amd.com>	2022-02-11 20:06:40 -06:00
zjing14	b53e9d08ed	Batched GEMM for fp16 (#79) ... * prepare host for batched_gemm * init commit of batched kernels * fixed * refine transform with freeze * m/n padding * fixed a bug; clean * add small tiles * clean * clean code * clean code * add nt, tn, tt layout * add missing file * use StaticBufferTupleOfVector instead * add reference_batched_gemm * fixed a macro	2022-02-11 09:36:52 -06:00
Chao Liu	823657ed12	GEMM+Bias+ReLU+Add (#76) ... * tweak conv for odd C * update script * clean up elementwise op * fix build * clean up * added example for gemm+bias+relu+add * added example for gemm+bias+relu * add profiler for gemm_s_shuffle; re-org files * add profiler * fix build * clean up * clean up * clean up * fix build	2022-02-06 22:32:47 -06:00