3 Commits

Author	SHA1	Message	Date
Illia Silin	6dcca8b18c	Adding Resnet50 test to Performance tests (#268) ... * add resnet50 test to performance tests * add blanks before gpu_arch in log files * add resnet50 test with N=4 and process its results * add ROCM and HIP versions to test tables * uncomment the sql queries * fix script syntax in jenkinsfile [ROCm/composable_kernel commit: 1677cf705e]	2022-06-02 18:16:59 -05:00
Chao Liu	8efcb80fa5	GEMM+Bias+ReLU+Add (#76) ... * tweak conv for odd C * update script * clean up elementwise op * fix build * clean up * added example for gemm+bias+relu+add * added example for gemm+bias+relu * add profiler for gemm_s_shuffle; re-org files * add profiler * fix build * clean up * clean up * clean up * fix build [ROCm/composable_kernel commit: 823657ed12]	2022-02-06 22:32:47 -06:00
Chao Liu	b827099a27	FP16 data in-register transpose (#41) ... * start fixing 16bit data packing * adding StaticTensor * adding StaticTensor * adding StaticTensor * add missing constexpr * adding static tensor * adding static tensor * adding transpose * add inline asm for transpose 2x2 of half_t * add general transpose_vectors(), but have unnecessary register initialization using v_mov * fix unnecessary register initialization in transpose_vector by using more pass-by-reference * add hardcoded logic for NHWC wrw * improve asm for v_pack * make ThreadwiseTensorSliceTransfer_v3r2 support any tensor * tweak * reorganize file [ROCm/composable_kernel commit: b491ebf384]	2021-11-15 10:05:58 -06:00