Commit Graph

1105 Commits

Author SHA1 Message Date
Qianfeng Zhang
ac0e593e0d Use compiler builtin directly in f_silu for float type 2026-06-23 09:20:57 +00:00
Qianfeng Zhang
31c21c74d8 Code re-arrangement in pipeline 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
eb2564fe46 Update the seqlen_k_curr inside the first gemm loop 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
40683ee932 Rename the performance measurement scripts 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
79fdd564b8 Add support for WarpGem-16x16x32 in QK-BlockGemm (which enables using ds_write/read_b128 for K 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
1986d8c578 Update in K-Lds laying-out to consider for both WarpGemm-32x32x16 and WarpGemm-16x16x16 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
6dd83b2a5a Use 16x16x16 WarpGemm 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
7153a99dd4 Using __builtin_amdgcn_rcpf in siLU function 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
fb89a013b7 Combine minus with scale_s 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
23e80a5964 Move silu calculation to gemm1 iteration and try to interleave gemm_1 and silu 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
f40d68c1a9 Update in using masking for the case where kMasking is false and kPadSeqLenK is true 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
95b9a277ac Fix in generate_instances.py and re-generated the instances 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
e5fb03a4aa Back to use exp() instead of exp2() since exp() in ck_tile using fast __builtin_amdgcn_exp2f() 2026-06-23 09:19:46 +00:00
Qianfeng Zhang
266e7bc8e9 Use kN0=64 to save vgprs 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
8f7a97fe02 Fix the script name 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
bace12feac Fix in GetTileRangeAlongX 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
7a7c17802a Add script compare_with_triton_2.sh for measuring the jagged cases of seqlen 1024/2048/4096/8192/16384/32768 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
e731437af1 Change gemm0 to iterate along kN0 so that BlockGemm can overlap with maksing and siLu 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
8da21d9cde Fix the GetTileRangeAlongX() to align with the hstu masking definition when both causal=true and local=true 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
065776d42d Remove un-needed __builtin_amdgcn_sched_barrier(0) 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
63acd4638b Use shared ring Lds buffers for K/V to avoid over-lapping between first-K/last-V or last-K/first-V 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
58090fe730 Tiny codes simplification in pipeline 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
ec14e9df3e Remove one line of __builtin_amdgcn_sched_barrier(0) 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
c0609d49cd Fix the integer overflow in total_flops calculation 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
1efb2a8f38 Add scripts for comparing with triton 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
70b4aa310f Use exp2() to calculate exp() for better performance 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
45019fd5fd Remove the comparing of row/col to max_uih_len in masking 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
ad10a2dd53 Use kM0=128 kN0=64 to completely remove the vgprs spilling 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
8b2948b31e Split HstuBlockMasking into HstuBlockMaskWithLocal and HstuBlockMaskNoLocal to save vgprs for non-local situations 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
fafb375122 Use packed cast_tile for fp16 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
6686c7af44 Update to partially reduce the register spilling 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
459c5565d4 Add IsFirstVLdsBufferOverlapLastKLdsBuffer() check to reduce call of s_barrier() 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
8a6c2591b0 Update the in pipeline codes 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
d360c61200 Fix in calculation of total_flops and update benchmark scripts 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
251136cca7 Add output of estimated TFLOPS 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
644ea27e0e Update to the scripts and error thresholds 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
2a71304bbb Tune the input initialization to avoid over-flow in silu 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
9c2dbf8d64 Add benchmark_hstu_attention.sh 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
cdb0704377 Add several verification test cases 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
beb6fa8cc1 Fix in kernel and forward dispatch for jagged mode 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
24822a4898 Fix in hstu-attention pipeline (which makes some testing cases passed) 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
50b0af257c Fixes and updates 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
72774b718b Change in HstBlockMasking and kernel/reference codes for using masking 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
74a0ec4609 Fix and change in example 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
450494945f Add hstu attention kernel implementation, instances and interfaces (building succeeded) 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
e6b6323b67 fix the jagged mode tensor access in reference_hstu_attention 2026-06-23 09:17:26 +00:00
Qianfeng Zhang
a19f73c305 Initial reference implementation of hstu attention 2026-06-23 09:17:23 +00:00
Enrico Degregori
2733e75900 [rocm-libraries] ROCm/rocm-libraries#6565 (commit d41715e)
[CK Tile] Async support pipeline V3

## Motivation

Optimize pipeline V3 for gfx950 by enabling buffer load to lds (async
pipeline)

## Technical Details

- Add `Async` bool to `Problem` struct to enable async pipeline in
existing one
- Add `static_move_ys` to load transpose. This generates offset in
assembly instructions saving registers
- Add `is_valid` to `async_get_vectorized_elements`. Before hard coded
to true. It allows to support padding
- Remove unnecessary restrictions to `is_a_load_tr` and `is_b_load_tr`
(wider use of lds load transpose on gfx950)
- Integrate async support in existing V3 pipeline (avoid pipelines
duplication)
- Create policy to support both async and default cases. This could be
used by any async pipeline (next steps)
- Define `wg_attr_num_access` separately for A and B. This allows to
optimize ds_read instruction width for cases when one matrix is
transposed and the other is not. Before in such cases, `ds_read_b64` was
used instead of `ds_read_b128`
- Add test for V3 async. Currently only supporting cases with A and B
having the same type

## Test Plan

New test `test_ck_tile_gemm_pipeline_compv3_async`

## Submission Checklist

- [x] Look over the contributing guidelines at
https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.
2026-06-19 06:57:14 +00:00
Ville Pietilä
60b276647b [rocm-libraries] ROCm/rocm-libraries#8157 (commit b0d9d39)
[CK Tile] Rule-based configuration generation in CK
 Dispatcher codegen (#8157)
MIME-Version: 1.0
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## Motivation

The CK Tile Dispatcher code generation for CK Tile Profiler relies on
flat JSON files to list the generated configurations. This approach has
the following problems

- The JSON files are verbose
- The JSON files get easily out of sync with the CK Builder .config
files from which they were generated from.
- The JSON file based configuration make it hard to list explicitly the
rules that govern the instance generation.

## Technical Details

Replaced the JSON files with a rule based configuration. To preserve the
existing functionality, the `profiler` and the `tests` instance sets are
generated directly from the CK Builder config files. The JSON config
files are removed from source control, and the "on-the-fly" generation
guarantees that the Dispatcher codegen uses up to date configurations.

This is PR introduces six different rule sets for the CK Tile Dispatcher
code generation

1. `profiler`: matches with the old JSON set of profiler configurations.
2. `tests`: matches with the old JSON set of tests configurations.
3. `full`: full configuration set created from a rule-based config
selection
4. `full-tests`: a subset of `full` for generating configurations for
convolution integration tests.
5. `tiny`: a subset of `full-tests` to produce the minimal set of
configurations to test the Dispatcher codegen.
6. `default`: the default rules, which corresponds to the existing
heuristic rules for configuration selection. This ensures that ML based
kernel selection doesn't get broken.

The main use of the `full` rule set is to define a reasonable solution
space for the possible implicit GEMM configurations. We start from the
configurations that allowed by the device architecture. The `full` rule
set defines the relevant tile sizes for each convolution direction. From
the tile size we have a curated mapping to the number of waves over the
different GEMM axes, i.e., we describe how many waves each GEMM
dimensions corresponds to. The GEMM-K wave tile dimension can be
computed from the other parameters and does not need to be listed
explicitly.

An orthogonal axis to the tiling strategy is the vectorization strategy.
This mainly defined by the data type and hardware as in general, we want
to use the maximum possible load widths. The maximum sizes for each
convolution direction variant are defined by the implicit GEMM matrix
dimensions. For cases where have a low number of channels per
convolution group, we need smaller vector load sizes. These are captured
by the `VecStrategy` enumeration in the codegen rules.

The problem with the rule based configuration selection is that we "over
generate" configurations. The old JSON configurations compose
approximately 25% of all configuration that the `full` rule set creates.
The additional configurations are valid, but they many not provide any
performance benefits. Hence, we keep the `profiler` and `tests` rule set
for now to avoid building an excessive amount configurations by default.
The `full` rule set can be taken into use by specifying CMake
configuration flag `-D DISPATCHER_RULE_SET=full`. By default, the
`tests` rule set is used, i.e., we don't change the existing bahaviour.

## Test Plan

Added a new stage in the CI/CD pipeline that ensures the Dispatcher
codegen rules are up to date. Otherwise the functionality is covered by
the existing CI/CD tests. There are no functional changes to the
convolution kernels. Only how the different instances are generated.

## Test Result

If the CK Tile conv instances build without errors, the Dispatcher
codegen is generating valid code. If all tests in CI/CD pipeline are
passing, the Dispatcher codegen generates valid instances.

## Submission Checklist

- [x] Look over the contributing guidelines at
https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.
2026-06-18 01:22:50 +00:00
damien-lejeune
5bebfd460f [rocm-libraries] ROCm/rocm-libraries#8492 (commit 46b6a06)
Add tile size for FMHA batch prefill bf16 for MI308X

## Motivation

Adding a tile size adapted to MI308X, for the FMHA Batch Prefill BF16
input type case

## Technical Details

N/A

## Test Plan

Benchmarking from the Aiter side with:

```
python3 op_tests/test_batch_prefill.py  -s 8000 -p 1 -q 4 -k 1 --head_dim 256 -c true -d bf16 --input_dtype bf16 --quant_method none --kv_layout linear -t sglang -l 0.0 --return_lse false --profile
```

## Test Result

We see an improvement with the new tile size on MI308X (both with PLT
mode OFF and ON)

## Submission Checklist

- [X] Look over the contributing guidelines at
https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.

Co-authored-by: Damien Lejeune <damien.lejeune@amd.com>
2026-06-17 06:22:26 +00:00