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da8f48c6d652a7a44bf7cf5a82f580025dbb8516
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20 Commits

Author SHA1 Message Date
Chao Liu
da8f48c6d6 Use DynamicBuffer instead of raw pointer (#32) 
* Use DynamicBuffer to hold raw pointer (to global and LDS memory)

* add workaround for compiler issue (inefficient ISA) of ds_write for int8x4, int8x8, int8x16

[ROCm/composable_kernel commit: 78b987fbd6]
 2021-05-12 13:10:42 -05:00
Chao Liu
ce4662dbda No raw index calculation (#31) 
* Replace most raw index calculation to coordinate transformation
* Overhaul blockwise and threadwise GEMM
* Overhaul driver for gridwies GEMM kernel

Co-authored-by: Jing Zhang <jizhan@amd.com>

[ROCm/composable_kernel commit: 01055d95d9]
 2021-05-11 00:09:25 -05:00
Chao Liu
b4dbf677ce Dynamic tensor descriptor (#24) 
* support dynamic tensor descriptor

* use buffer load OOB feature for padding case

* add navi support

* add int8x4 inference kernel

Co-authored-by: Chao Liu <chao@ixt-rack-81.local.lan>
Co-authored-by: Jing Zhang <jizhan@amd.com>

[ROCm/composable_kernel commit: fcbb978828]
 2021-03-25 13:51:11 -05:00
Chao Liu
0eb214d1cd Code clean up (#20) 
* tuning para,

* testing on v100

* add fp16

* remove deprecated tensor descriptor

* sync with miopen

* update build script

Co-authored-by: Jing Zhang <jizhan@amd.com>

[ROCm/composable_kernel commit: 5c7cec1115]
 2020-06-23 20:31:27 -05:00
Chao Liu
8b51bc4b1d Added bwd data v3r1 v4r1, tweaking v1 (#10) 
* Added bwd data v3r1: breaking down compute into a series of load balanced GEMM, and launch in a single kernel
* Added bwd data v4r1: like v3r1, but launch GEMMs in multiple kernels
* Tweaked v1r1  and v1r2 (atomic) on AMD GPU

[ROCm/composable_kernel commit: c5da0377fb]
 2020-01-20 10:20:03 -06:00
Chao Liu
3799741fee backward data (#7) 
* enabled atomic add in tensor copy
* added gridwise GEMM
* added backward data conv using GEMM + atomic
* added backward data conv using GEMM, no atomic


[ROCm/composable_kernel commit: 8f5f64960e]
 2019-12-03 01:16:12 -06:00
Chao Liu
08f130fed1 Refactor for MIOpen integration (#4) 
Refactor, so can bring multi-index transformation and padding support into MIOpen

[ROCm/composable_kernel commit: 52c3fe05be]
 2019-10-11 11:37:31 -05:00
Chao Liu
0342a42f47 enable hip compiler flag: -amdgpu-enable-global-sgpr-addr 
[ROCm/composable_kernel commit: f58bf38445]
 2019-09-17 17:34:39 -05:00
Chao Liu
dd6fef3b9e add script for doing Jack's ISA injection hack 
[ROCm/composable_kernel commit: 0c83df668f]
 2019-08-21 14:29:13 -05:00
Chao Liu
dc2cdacd15 refactored implicit gemm v1r3 
[ROCm/composable_kernel commit: 284e7bb317]
 2019-07-29 15:25:38 -05:00
Chao Liu
360f15cf24 refactored implicit gemm v1r3 
[ROCm/composable_kernel commit: efd419ecbe]
 2019-07-29 15:01:01 -05:00
Chao Liu
3f33abf401 update compile script 
[ROCm/composable_kernel commit: c15ff3c825]
 2019-07-03 16:03:12 -05:00
Chao Liu
99fc474d24 tested on P100 
[ROCm/composable_kernel commit: dab2938937]
 2019-06-27 15:46:09 -05:00
Chao Liu
11c6b2ab9a change build 
[ROCm/composable_kernel commit: c82b833d8e]
 2019-06-12 10:47:25 -05:00
Jing Zhang
b6d7e5fd48 ds_read_offset 
[ROCm/composable_kernel commit: 49d5af1002]
 2019-04-26 15:55:26 -05:00
Chao Liu
35140bbc9e enabled ds_read_b128 and ds_write_b128 on hip c++ 
[ROCm/composable_kernel commit: e624df922d]
 2019-04-09 19:05:44 -05:00
Chao Liu
008c584abb Merge branch 'master' into inline_asm_v2 
[ROCm/composable_kernel commit: 605afd0fb6]
 2019-04-04 18:40:23 -05:00
Chao Liu
770c141f35 add script to extrac asm on hip 
[ROCm/composable_kernel commit: 6166233e05]
 2019-04-03 10:36:18 -05:00
Chao Liu
9d61f2597a add cuda extract_asm script 
[ROCm/composable_kernel commit: e6c86f81b5]
 2019-04-02 20:26:58 -05:00
Chao Liu
fdb7d41661 cleaning up dead code 
[ROCm/composable_kernel commit: bdbc0eaad1]
 2019-04-02 17:58:44 -05:00