mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-04-19 14:29:05 +00:00
920acd2c12
[CK] [CK_Tile] Add GroupConv to Kernel Dispatcher ## Motivation This PR adds CK Tile group convolution (forward, backward-data, backward-weight) support to the kernel dispatcher, matching and unifying with the existing dispatcher GEMM infrastructure in architecture and usability. The dispatcher provides a unified kernel dispatch system with both C++ and Python frontends, and until now only supported GEMM operations. This PR enables framework integrators to use the same declarative kernel workflow for convolutions as they do for GEMM: declare kernels, build a registry JIT, select kernels within the registry at runtime, and dispatch to GPU. Future PRs will include runtime kernel selection heuristics for autotuning of kernel parameters based on (problem, hardware arch). ## Technical Details Grouped convolution support has been added to the CK Tile Dispatcher with generated_conv_backend.hpp enabling dispatcher.run(in, wei, out, problem) for all 6 conv variants (fwd/bwdd/bwdw x 2D/3D), runtime heuristic kernel selection, and GroupedConvKernelKey with full ConvConfigBase fields. Python side adds parallel JIT via registry.build(max_workers) and heuristic registry.select(). Includes 7 C++ and 6 Python examples covering all directions with CPU reference validation, and shared infrastructure improvements (BaseRegistry CRTP, structured exceptions). As a sanity check, JIT compile times for a single kernel remains the same and for multiple kernels there is better parallelism: Kernels | 1 worker | 8 workers 1 | 7.7 s | 7.7 s 2 | 15.9 s | 8.2 s 4 | 33.4 s | 9.7 s 6 | 52.3 s | 10.2 s ## Test Plan 145 ephemeral unit tests have been added to test basic functionality. All 30 examples/integration tests run end-to-end on gfx950 (MI350): 7 C++ conv, 7 C++ GEMM, 6 Python conv, 10 Python GEMM. CPU reference validation for forward, backward-data, and backward-weight (2D) in both C++ and Python examples pass. ## Test Result 30 examples pass. Peak performance: 132 TFLOPS (Batch-32 forward 56x56), 53 TFLOPS (pointwise 1x1). CPU reference accuracy: max_abs_diff < 0.002 for all directions (fp16 vs fp32 reference). ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.
36 lines
1.4 KiB
C++
36 lines
1.4 KiB
C++
// Copyright (c) Advanced Micro Devices, Inc., or its affiliates.
|
|
// SPDX-License-Identifier: MIT
|
|
|
|
#pragma once
|
|
|
|
/// Full dispatcher header - includes ALL operation types.
|
|
/// For minimal includes, use the per-operation headers instead:
|
|
/// ck_tile/dispatcher_gemm.hpp -- GEMM only
|
|
/// ck_tile/dispatcher_conv.hpp -- Grouped Convolution only
|
|
|
|
// Core (needed by all ops)
|
|
#include "ck_tile/dispatcher/base_registry.hpp"
|
|
#include "ck_tile/dispatcher/dispatcher_error.hpp"
|
|
#include "ck_tile/dispatcher/example_args.hpp"
|
|
|
|
// GEMM
|
|
#include "ck_tile/dispatcher/kernel_key.hpp"
|
|
#include "ck_tile/dispatcher/kernel_config.hpp"
|
|
#include "ck_tile/dispatcher/kernel_decl.hpp"
|
|
#include "ck_tile/dispatcher/problem.hpp"
|
|
#include "ck_tile/dispatcher/kernel_instance.hpp"
|
|
#include "ck_tile/dispatcher/registry.hpp"
|
|
#include "ck_tile/dispatcher/dispatcher.hpp"
|
|
#include "ck_tile/dispatcher/json_export.hpp"
|
|
#include "ck_tile/dispatcher/arch_filter.hpp"
|
|
#include "ck_tile/dispatcher/backends/tile_backend.hpp"
|
|
#include "ck_tile/dispatcher/backends/generated_tile_backend.hpp"
|
|
#include "ck_tile/dispatcher/utils.hpp"
|
|
|
|
// Grouped Convolution
|
|
#include "ck_tile/dispatcher/grouped_conv_config.hpp"
|
|
#include "ck_tile/dispatcher/grouped_conv_problem.hpp"
|
|
#include "ck_tile/dispatcher/grouped_conv_kernel_decl.hpp"
|
|
#include "ck_tile/dispatcher/grouped_conv_registry.hpp"
|
|
#include "ck_tile/dispatcher/grouped_conv_utils.hpp"
|