ROCm/composable_kernel
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zjing14 2457224dc9 Hybrid direct + implicit GEMM forward convolution NCHWc v5r1 (#25) 
* Hybrid direct + implicit GEMM forward convolution NCHWc v5r1. Input tensor bypass LDS. Support fp32/fp16/int8

[ROCm/composable_kernel commit: 792a20fa5b]
2021-04-07 16:47:29 -05:00
..
conv_common.hpp
Dynamic tensor descriptor (#24)
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device_convolution_backward_data_implicit_gemm_v1r1_nchw_kcyx_nkhw.hpp
Dynamic tensor descriptor (#24)
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device_convolution_backward_data_implicit_gemm_v1r2_nchw_kcyx_nkhw.hpp
Code clean up (#20)
2020-06-23 20:31:27 -05:00
device_convolution_backward_data_implicit_gemm_v4r1_nchw_kcyx_nkhw.hpp
Dynamic tensor descriptor (#24)
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device_convolution_backward_data_implicit_gemm_v5r1_nhwc_kyxc_nhwk.hpp
Dynamic tensor descriptor (#24)
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device_convolution_forward_implicit_gemm_v4r1_nchw_kcyx_nkhw.hpp
Dynamic tensor descriptor (#24)
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device_convolution_forward_implicit_gemm_v4r4_nchw_kcyx_nkhw.hpp
Dynamic tensor descriptor (#24)
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device_convolution_forward_implicit_gemm_v4r4_nhwc_kyxc_nhwk.hpp
Dynamic tensor descriptor (#24)
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device_dynamic_convolution_forward_implicit_gemm_v4r4_nchw_kcyx_nkhw.hpp
Dynamic tensor descriptor (#24)
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device_dynamic_convolution_forward_implicit_gemm_v4r4_nhwc_kyxc_nhwk.hpp
Dynamic tensor descriptor (#24)
2021-03-25 13:51:11 -05:00
device_dynamic_convolution_forward_implicit_gemm_v5r1_nchw_kcyx_nkhw.hpp
Hybrid direct + implicit GEMM forward convolution NCHWc v5r1 (#25)
2021-04-07 16:47:29 -05:00
device_tensor.hpp
Code clean up (#20)
2020-06-23 20:31:27 -05:00
device.hpp
Code clean up (#20)
2020-06-23 20:31:27 -05:00
host_conv_bwd_data.hpp
Code clean up (#20)
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host_conv.hpp
Dynamic tensor descriptor (#24)
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host_tensor_generator.hpp
Code clean up (#20)
2020-06-23 20:31:27 -05:00
host_tensor.hpp
Dynamic tensor descriptor (#24)
2021-03-25 13:51:11 -05:00