mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-16 02:54:21 +00:00
1d9320c8f3
* Initial implementation:
- add new thread group transfer supporting transpose instruction
- refactor AB transfer to switch between thread and wave tiles methods
* Add some comments and remove explicit wave and lane calculations
* Remove compiler option for performance
* fp16 example: use tuned instance
* Missing cleanup
* Integrate wave transfer in existing gemm and batched gemm instances
* Add fast instances
* extend implementation for 8 bit datatypes
packed types not supported
* Address review comments
* Optimize pipeline v1 and re-introduce compiler option
* Disable wave tile approach for b scale gemm
* Fix for clang20
* Avoid code duplication of amd_global_load_transpose_to_vgpr function
[ROCm/composable_kernel commit: 440358c168]
66 lines
1.2 KiB
C++
66 lines
1.2 KiB
C++
// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2025, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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#include "ck/ck.hpp"
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namespace ck {
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#if CK_EXPERIMENTAL_BLOCK_SYNC_LDS_WITHOUT_SYNC_VMEM
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#ifdef __gfx12__
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__device__ void llvm_amdgcn_s_wait_dscnt(short cnt) __asm("llvm.amdgcn.s.wait.dscnt");
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#endif
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#endif
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__device__ void block_sync_lds()
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{
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#if CK_EXPERIMENTAL_BLOCK_SYNC_LDS_WITHOUT_SYNC_VMEM
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#ifdef __gfx12__
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llvm_amdgcn_s_wait_dscnt(0);
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asm volatile("s_barrier_signal -1\n\t"
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"s_barrier_wait -1");
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#else
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// asm volatile("\
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// s_waitcnt lgkmcnt(0) \n \
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// s_barrier \
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// " ::);
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__builtin_amdgcn_s_waitcnt(0xc07f);
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__builtin_amdgcn_s_barrier();
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#endif
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#else
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__syncthreads();
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#endif
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}
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__device__ void block_sync_lds_direct_load()
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{
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#ifdef __gfx12__
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asm volatile("\
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s_wait_loadcnt 0x0 \n \
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s_wait_dscnt 0x0 \n \
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s_barrier_signal -1 \n \
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s_barrier_wait -1 \
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" ::);
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#else
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asm volatile("\
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s_waitcnt vmcnt(0) \n \
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s_waitcnt lgkmcnt(0) \n \
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s_barrier \
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" ::);
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#endif
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}
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__device__ void s_nop()
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{
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#if 1
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asm volatile("\
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s_nop 0 \n \
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" ::);
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#else
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__builtin_amdgcn_sched_barrier(0);
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#endif
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}
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} // namespace ck
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