Illia Silin 86990558e3 Upgrade default compiler to ROCm6.3 (#1723) ...

* upgrade to rocm6.3 compiler

* Proposed solution to convnd test failures in ROCm 6.3

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Co-authored-by: Andriy Roshchenko <andriy.roshchenko@amd.com>

2024-12-05 17:29:12 -08:00

..

binary

Add grouped conv bwd weight multi d kernel (#1237)

2024-04-18 23:35:04 +02:00

convinvscale

Add a convinvscale op, related instances and examples (#1307)

2024-06-10 14:48:49 -05:00

convscale

Upgrade default compiler to ROCm6.3 (#1723)

2024-12-05 17:29:12 -08:00

convscale_add

Adding more instances of grouped convolution 3d forward for FP8 with ConvScale+Bias element-wise operation. (#1412)

2024-07-24 15:49:55 -05:00

convscale_reduce

Adding Instances and Examples for FP8-based Scaled Convolution and AMAX Reduction. (#1473)

2024-08-21 15:22:41 -07:00

convscale_relu

Adding more instances of grouped convolution 3d forward for FP8 with ConvScale element-wise operation and ReLU activation. (#1386)

2024-07-16 08:51:49 -07:00

dynamic_unary

Add dynamic elementwise op (#1426)

2024-10-26 15:22:37 +02:00

multi_AB

Add bilinear conv fwd and bwd data instances (#1164)

2024-02-13 11:49:05 +01:00

unary

Adding Missed Activation Functions for Grouped 2D/3D Convolutions (#1348)

2024-06-20 09:24:54 -05:00

CMakeLists.txt

Add dynamic elementwise op (#1426)

2024-10-26 15:22:37 +02:00

convnd_fwd_xdl_scaleadd_scaleadd_relu_bcasted_bias_fp16.cpp

Add bilinear conv fwd and bwd data instances (#1164)

2024-02-13 11:49:05 +01:00

convnd_fwd_xdl_scaleadd_scaleadd_relu_fp16.cpp

Add bilinear conv fwd and bwd data instances (#1164)

2024-02-13 11:49:05 +01:00

run_convnd_activ_dynamic_example.inc

Add dynamic elementwise op (#1426)

2024-10-26 15:22:37 +02:00

run_convnd_activ_example.inc

Add bilinear conv fwd and bwd data instances (#1164)

2024-02-13 11:49:05 +01:00