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bd96ac9742
* Multiple d, initial commit * Check Ds Layout * Readme and clang format * Update branch & conflicts * Multiple D - fix clang-formatter * Rename elemetwise_op * Fix CI * Code review part1 * Remove printf * Remove unnecessary comment * Add new tests with Col layout * Review part 2 * Added support for Multiple D GEMM * Update comment * Remove maybe_unused * Clang-format * Review part 3 * Add comment to function * Add comment to function: another * Take number of params for a refrence function * Remove additional d param for 0 tensor * Change name of function * Fix CI fails
86 lines
3.3 KiB
C++
86 lines
3.3 KiB
C++
// SPDX-License-Identifier: MIT
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// Copyright (c) 2024-2025, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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#include <string>
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#include "ck_tile/core.hpp"
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#include "ck_tile/host/kernel_launch.hpp"
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#include "ck_tile/ops/gemm/kernel/batched_gemm_kernel.hpp"
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#include "ck_tile/ops/elementwise/unary_element_wise_operation.hpp"
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#define CK_TILE_PIPELINE_COMPUTE_V3 1
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#define CK_TILE_PIPELINE_MEMORY 2
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#define CK_TILE_PIPELINE_COMPUTE_V4 3
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#ifndef CK_TILE_PIPELINE_DEFAULT
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#define CK_TILE_PIPELINE_DEFAULT CK_TILE_PIPELINE_COMPUTE_V3
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#endif
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#if(CK_TILE_PIPELINE_DEFAULT == CK_TILE_PIPELINE_MEMORY)
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#define GEMM_PIPELINE ck_tile::GemmPipelineAgBgCrMem
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#define UNIVERSAL_GEMM_PIPELINE ck_tile::BaseGemmPipelineAgBgCrMem
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#define GEMM_PIPELINE_SCHEDULER ck_tile::GemmPipelineScheduler::Interwave
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#elif(CK_TILE_PIPELINE_DEFAULT == CK_TILE_PIPELINE_COMPUTE_V3)
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#define GEMM_PIPELINE ck_tile::GemmPipelineAgBgCrCompV3
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#define UNIVERSAL_GEMM_PIPELINE ck_tile::BaseGemmPipelineAgBgCrCompV3
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#define GEMM_PIPELINE_SCHEDULER ck_tile::GemmPipelineScheduler::Intrawave
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#elif(CK_TILE_PIPELINE_DEFAULT == CK_TILE_PIPELINE_COMPUTE_V4)
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#define GEMM_PIPELINE ck_tile::GemmPipelineAgBgCrCompV4
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#define UNIVERSAL_GEMM_PIPELINE ck_tile::BaseGemmPipelineAgBgCrCompV4
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#define GEMM_PIPELINE_SCHEDULER ck_tile::GemmPipelineScheduler::Intrawave
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#else
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#error "unsupported CK_TILE_PIPELINE_DEFAULT value"
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#endif
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template <typename DataType>
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struct BatchedGemmTypeConfig;
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template <>
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struct BatchedGemmTypeConfig<ck_tile::half_t>
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{
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using ADataType = ck_tile::half_t;
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using BDataType = ck_tile::half_t;
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using AccDataType = float;
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using CDataType = ck_tile::half_t;
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};
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using Types = BatchedGemmTypeConfig<ck_tile::half_t>;
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// Specific type aliases for easy access
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using ADataType = Types::ADataType;
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using BDataType = Types::BDataType;
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using AccDataType = Types::AccDataType;
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using CDataType = Types::CDataType;
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auto create_args(int argc, char* argv[])
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{
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ck_tile::ArgParser arg_parser;
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arg_parser.insert("m", "512", "m dimension")
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.insert("n", "1024", "n dimension")
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.insert("k", "2048", "k dimension")
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.insert("stride_a", "0", "Tensor A stride")
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.insert("stride_b", "0", "Tensor B stride")
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.insert("stride_c", "0", "Tensor C stride")
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.insert("a_layout", "R", "A tensor data layout - Row by default")
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.insert("b_layout", "C", "B tensor data layout - Row by default")
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.insert("c_layout", "R", "C tensor data layout - Row by default")
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.insert("batch_stride_a", "1048576", "Batch A stride")
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.insert("batch_stride_b", "2097152", "Batch B stride")
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.insert("batch_stride_c", "524288", "Batch C stride")
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.insert("batch_count", "8", "Batch count")
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.insert("v", "2", "0. No validation, 1. Validation on CPU, 2. Validation on GPU")
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.insert("prec", "fp16", "data type. fp16/bf16/fp8/bf8")
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.insert("warmup", "50", "number of iterations before benchmark the kernel")
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.insert("repeat", "100", "number of iterations to benchmark the kernel")
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.insert("timer", "gpu", "gpu:gpu timer, cpu:cpu timer")
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.insert("split_k", "1", "splitK value");
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bool result = arg_parser.parse(argc, argv);
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return std::make_tuple(result, arg_parser);
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}
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// host API
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float batched_gemm(const ck_tile::BatchedGemmHostArgs& args, const ck_tile::stream_config& s);
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