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https://github.com/ROCm/composable_kernel.git
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8eff4d62b6
* Format * Format * Format * Remove const * Use the right template * Format * Format * add row/col instances * Add missing file * fixed * Format * Updates * Format * fixed rrr layout * Format * Update test and embed modules * Restore older version * Update year * Set -fPIC * Format * Use double for isnan * rename host folder to codegen + minor fix * add codegen CI test * add option to build components without building CK * fix the groovy syntax * fix typo * use the correct function for the codegen stage --------- Co-authored-by: Jing Zhang <jizha@amd.com> Co-authored-by: Illia Silin <98187287+illsilin@users.noreply.github.com> Co-authored-by: illsilin <Illia.Silin@amd.com>
50 lines
1.4 KiB
C++
50 lines
1.4 KiB
C++
// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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#include <string>
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namespace ck {
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namespace host {
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namespace operation {
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struct TileDesc
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{
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int block_size = 0;
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int m_per_block = 0;
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int n_per_block = 0;
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int k_per_block = 0;
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int ak1 = 0;
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int bk1 = 0;
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int m_per_XDL = 0;
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int n_per_XDL = 0;
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int m_Xdl_per_wave = 0;
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int n_Xdl_per_wave = 0;
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int num_gemmk_prefetch_stage = 0;
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};
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struct BlockTransferDesc
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{
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std::string thread_cluster_length = "";
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std::string thread_cluster_arrange_order = "";
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std::string src_access_order = "";
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int src_vec_dim = 0;
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int src_scalar_per_vector = 0;
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int dst_scalar_per_vector_k1 = 0;
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int lds_add_extra_dim = 0;
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};
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struct CShuffleDesc
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{
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int m_Xdl_per_wave_per_shuffle = 0;
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int n_Xdl_per_wave_per_shuffle = 0;
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};
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struct CBlockTransferDesc
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{
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std::string cluster_lengths_m_block_m_wave_m_per_Xdl_n_block_n_wave_n_per_Xdl = "";
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int scalar_per_vector_n_wave_n_per_Xdl = 0;
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};
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} // namespace operation
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} // namespace host
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} // namespace ck
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