mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-03 13:11:25 +00:00
1e77695fe8
* Pass hdim to tile_example_fmha_fwd in fp8 tests
* Add WMMA support to fwd FMHA pipelines
* Tune tile sizes a bit for less spilling
fp16 256 is still quite slow
* Fix Q grad tile distribution for warp size = 32 and hdim >= 256
With AccDataType = float and warp size = 32, K0 becomes 0, K repeat is required to correcty distribute the tile.
* Use code based on BlockDropout in BlockDropoutBwd
* Fix split KV combine kernel for gfx12 (warp size 32) and make it more universal
* Fix LSE LDS tensor descriptors: kMaxSplits and kM0 were swapped, it worked on gfx9
because they both equal to 8 while on gfx12 they are 8 and 4;
* Fix Oacc LDS tensor descriptor: it was transposed even though its shape=[4 * kM0, kN1],
it worked on gfx9 because 4 * kM == kN1 == 32;
* Removing these hidden dependecies allows to support:
* any number of warps (power-of-2), not only 4;
* kN1 = 16, not only 32;
* any number of splits;
* Rename ids like o_acc_4 and Oacc4 to eliminate confusion: kNumWarps doesn't have to be 4 now
* Replace hard-coded kN1 in dispatch code with the requested tile size
* Add gfx12-specific tile sizes for split KV
* Pass GPU architecture to kernel generation scripts
This is still a temporary solution.
* Build and run FMHA CI tests for gfx12
* Fix issue after merging
* Fix bwd tile sizes
The current pipelines always read only one tile K and V tile, this
requires bk0 == bhdq and bk2 == bhdv (kK0 == kQKHeaddim and
kK2 == kVHeaddim).
* Use hardware f32->f8 on gfx12, remove v_perm
__builtin_amdgcn_perm is not needed because
__builtin_amdgcn_cvt_pk_fp8_f32 allows to specify which word (16 bit of
32-bit dword) is used to store results (two f8 values).
* Update changelog
* Add WMMA support to pagedkv
* Fix scripts after rebasing
* Support 16x16 (MFMA, WMMA) and 32x32 (MFMA) tiles in fwd and bwd BlockDropout
Add comments with dropout implementation details
Fix performance regression of fwd+dropout
* Remove some usage of type punning (reinterpret_cast with ref or ptr) in Philox;
* "scalarize" seed and offset, they may come either from kernel args or from device memory
(presumably loaded with vector loads).
These changes help the compiler to procude more optimal code and reduce register spilling.
Use WarpGemmDispatcher instead of explicit WarpGemmMfma... to get CWarpDstrEncoding
Use code based on BlockDropout in BlockDropoutBwd
Refactor BlockDropout (fwd)
Implement BlockDropout (fwd) for WMMA
Originally BlockDropout only supported 32x32 tiles (IsWG32 = true),
this version supports 16x16 tiles.
If MPerBlock > MWarp * 16, it can generate numbers for two 16x16 tiles, similarly
to BlockDropoutBwd.
Implement BlockDropoutBwd for WMMA
Remove MakeRandValLds* functions unused in BlockDropoutBwd
Remove unused Run overload from BlockDropoutBwd
* Fix regression with philox seed and offset when they exceed 32-bit int
__builtin_amdgcn_readfirstlane works with 32-bit values, seed and offset
are 64-bit so they get truncated.
* Fix names after cherry-picking
* Fix selection of a fallback tile based on bm0
The assumption that the largest bm0 == 128 is not always true for
current fp32 tiles.
* Do not use filters related to qr_async_trload
They disable tiles/pipelines which are valid for gfx12.
* Use different dstr encoding when C is transposed
* Do not call GetQKBlockGemm (and hence WarpGemmDispatcher) in host code
Some WarpGemmDispatcher instantiations are defined only
for specific archs and undefined on host.
Calculations related to sched barriers are moved from Pipeline's public
fields into pipeline's operator().
* Fix incorrect name WarpGemmMfmaFp8Fp8F32M32N32K16SwizzleBTransposedCDistribution
Correct name is WarpGemmMfmaFp8Fp8F32M32N32K32SwizzleBTransposedCDistribution
because it's 32x32x16 with IterateK = 2 so K = 32, also all tiles used
in codegen scripts are 32, 32, 32.
* Generalize usages of WarpGemmDispatcher for MFMA and WMMA
WarpGemmMfmaFp8Fp8F32M32N32K32SwizzleBTransposedCDistribution is still
used explicitly becaus of swizzle factor = 4.
* Mark has_load_tr as maybe_unused
There are no transpose loading for RDNA.
* Remove CK_TILE_USE_MFMA/WMMA from fmha-related code
* Detect BlockSize on host based on warp size of the current device
If kBlockSize == kNumWarps * get_warp_size(), the kernel is launched with
kBlockSize / 2 because on host get_warp_size() == 64 always.
* Fix calculation of grid size for combine kernel with warp size = 32
* Add missing includes and header
* Support multiple archs in one binary for fwd
* Support multiple archs in one binary for fwd_splitkv, fwd_appendkv, pagedkv_prefill
* Support multiple archs in one binary for bwd
* trload kernels are compiled only for gfx950;
* instances with padding are checked after instances without padding so
they can be used as fallbacks (similarly to fwd);
* Extract common code from register_traits
* Revert "Fix regression with philox seed and offset when they exceed 32-bit int"
To simplify merging , the proper fix is in develop already.
* Support new numerical d paddings in trait ordering checks
* Build fp32 tests only on gfx9
* Do not use hardcoded M0 = 64 for dot bwd kernel
* Use textwrap.indent from standard library
* Make fp8 pipelines on gfx12 consistent with gfx9
* Update tests for current pipelines
* Make ninja check more responsive in CI
ninja buffers output so this job looks hanging.
* Support fp8fp32 by limiting O vector size
The fp32 output type requires storing 8 * sizeof(float) = 32 bytes,
which is not implemented (here 8 is the number of C values per lane for
v_wmma_f32_16x16x16...).
* Remove unused cmake options
* Unify including amd_buffer_addressing.hpp/_builtins.hpp
* Temporarily use amd_buffer_addressing.hpp on >=gfx10
amd_buffer_addressing_builtins.hpp uses inline asm for loads/stores
which is not compatible with >=gfx10:
* 1 scalar for exec masks instead of 2,
* gfx12 uses different instruction names etc.
* Update asm in bf16 conversions to work with warp 32
* Do not generate splitkv/appendkv with vlayout=col for consistency with fwd
* Add arch tags to kernels/host funcs, compile for each arch separately
* Add kM0 to fmha_bwd_dot_do_o kernel name to match filename
* Add workaround for miscompilation of bwd with padded hdim
SWDEV-559729: v_wmma instructions can be incorrectly placed in divergent
branches used to store padded tensors (when some lanes are inactive due
to padding). Inline asm with dummy dependencies on VGPRs of the tensors
prevents the compiler doing this.
* Fix add_gtest_executable for absolute paths
Some tests (like gemm_tile_engine) pass absolute paths to source files.
In CI the branch name is a part of the root dir, and if the branch name
contains "wmma", "xdl" etc., files can be incorrectly excluded.
* Run only hdim 128 smoke tests for fp8fp32
There are no instances for hdim 64 and 256.
* Format py with ruff to simplify merging develop
* Fix incorrect var name
* Codegen for gfx9,gfx950 when --targets is not specified
Aiter and Pytorch require changes for passing their targets to the codegen scripts.
With this temporary solution the files are generated but not all of them
have to be really built (depending on the used --offload-arch=).
* Combine arch-related values into ArchTrait
This more centralized approach removes duplication of various formatting templates.
* Try a workaround for Jenkins error "groovyjarjarasm.asm.MethodTooLargeException: Method too large"
Some code is extracted into a function.
283 lines
8.9 KiB
C++
283 lines
8.9 KiB
C++
// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2025, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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#if defined(__gfx908__) || defined(__gfx90a__) || defined(__gfx942__) || defined(__gfx950__) || \
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defined(__gfx9_4_generic__)
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#define __gfx9__
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#endif
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#if defined(__gfx942__) || defined(__gfx950__) || defined(__gfx9_4_generic__)
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#define __gfx94__
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#endif
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#if defined(__gfx1030__) || defined(__gfx1031__) || defined(__gfx1032__) || \
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defined(__gfx1034__) || defined(__gfx1035__) || defined(__gfx1036__) || \
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defined(__gfx10_3_generic__)
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#define __gfx103__
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#endif
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#if defined(__gfx1100__) || defined(__gfx1101__) || defined(__gfx1102__) || \
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defined(__gfx1103__) || defined(__gfx1150__) || defined(__gfx1151__) || \
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defined(__gfx1152__) || defined(__gfx11_generic__)
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#define __gfx11__
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#endif
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#if defined(__gfx1200__) || defined(__gfx1201__) || defined(__gfx12_generic__)
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#define __gfx12__
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#endif
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#include "hip/hip_version.h"
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#ifndef CK_TILE_DONT_USE_HIP_RUNTIME_HEADERS
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#include "hip/hip_runtime.h"
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#include "hip/hip_fp16.h"
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#endif
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#ifdef __HIPCC__
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#define CK_TILE_HOST inline __host__
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#define CK_TILE_DEVICE inline __device__
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#define CK_TILE_HOST_DEVICE inline __host__ __device__
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#define CK_TILE_DEVICE_EXTERN __device__
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#define CK_TILE_HOST_DEVICE_EXTERN __host__ __device__
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#else
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#define CK_TILE_HOST inline
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#define CK_TILE_DEVICE inline
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#define CK_TILE_HOST_DEVICE inline
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#define CK_TILE_DEVICE_EXTERN
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#define CK_TILE_HOST_DEVICE_EXTERN
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#endif
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// implementing the "memory address space" attribute
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// https://llvm.org/docs/AMDGPUUsage.html#amdgpu-address-spaces-table
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// WA for https://github.com/ROCm/composable_kernel/issues/1946
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#if 0
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#define CK_TILE_GENERIC_ADDR __attribute__((address_space(0)))
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#define CK_TILE_GLOBAL_ADDR __attribute__((address_space(1)))
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#define CK_TILE_LDS_ADDR __attribute__((address_space(3)))
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#define CK_TILE_BUF_RES_ADDR __attribute__((address_space(8)))
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#else
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#define CK_TILE_GENERIC_ADDR
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#define CK_TILE_GLOBAL_ADDR
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#define CK_TILE_LDS_ADDR
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#define CK_TILE_BUF_RES_ADDR
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#endif
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#ifndef CK_TILE_USE_CUSTOM_DATA_TYPE
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#define CK_TILE_USE_CUSTOM_DATA_TYPE 0 // custom data type will generate extra move/bfi code
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#endif
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#define CK_TILE_FLOAT_TO_BFLOAT16_STANDARD 0
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#define CK_TILE_FLOAT_TO_BFLOAT16_TRUNCATE_WITH_NAN 1
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#define CK_TILE_FLOAT_TO_BFLOAT16_TRUNCATE 2
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#define CK_TILE_FLOAT_TO_BFLOAT16_STANDARD_ASM 3
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#define CK_TILE_FLOAT_TO_BFLOAT16_RTA_ASM 4
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#ifndef CK_TILE_FLOAT_TO_BFLOAT16_DEFAULT
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#define CK_TILE_FLOAT_TO_BFLOAT16_DEFAULT CK_TILE_FLOAT_TO_BFLOAT16_TRUNCATE
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#endif
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#define CK_TILE_FLOAT_TO_FP8_STANDARD 0
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#define CK_TILE_FLOAT_TO_FP8_STOCHASTIC 1
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#ifndef CK_TILE_FLOAT_TO_FP8_DEFAULT
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#define CK_TILE_FLOAT_TO_FP8_DEFAULT CK_TILE_FLOAT_TO_FP8_STANDARD
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#endif
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// in the old rocm period, we have to use tuple array implementation to implement this
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// so turn on the _USE_TUPLE if meet compiler error, otherwise _USE_ARRAY by default.
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#define CK_TILE_STATICALLY_INDEXED_ARRAY_USE_ARRAY 0
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#define CK_TILE_STATICALLY_INDEXED_ARRAY_USE_TUPLE 1
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#ifndef CK_TILE_STATICALLY_INDEXED_ARRAY_DEFAULT
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#define CK_TILE_STATICALLY_INDEXED_ARRAY_DEFAULT CK_TILE_STATICALLY_INDEXED_ARRAY_USE_TUPLE
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#endif
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#define CK_TILE_THREAD_BUFFER_USE_ARRAY 0
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#define CK_TILE_THREAD_BUFFER_USE_TUPLE 1
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#ifndef CK_TILE_THREAD_BUFFER_DEFAULT
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#define CK_TILE_THREAD_BUFFER_DEFAULT CK_TILE_THREAD_BUFFER_USE_ARRAY
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#endif
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#ifndef CK_TILE_TUPLE_CTOR_WITH_INITIALIZER_LIST
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#if CK_TILE_THREAD_BUFFER_DEFAULT == CK_TILE_THREAD_BUFFER_USE_TUPLE
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// if using tuple-array as thread_buffer implementation, need to support {} brace init
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// ... with similiar behavior as array
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#define CK_TILE_TUPLE_CTOR_WITH_INITIALIZER_LIST 1
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#else
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#define CK_TILE_TUPLE_CTOR_WITH_INITIALIZER_LIST 0
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#endif
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#endif
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#ifndef CK_TILE_USE_LAUNCH_BOUNDS
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#define CK_TILE_USE_LAUNCH_BOUNDS 1
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#endif
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#ifndef CK_TILE_TIME_KERNEL
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#define CK_TILE_TIME_KERNEL 1
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#endif
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#define CK_TILE_MAX_THREAD_PER_BLOCK 256
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#define CK_TILE_MIN_BLOCK_PER_CU 2
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#ifndef CK_TILE_EXPERIMENTAL_USE_BUFFER_LOAD_OOB_CHECK_OFFSET_TRICK
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#define CK_TILE_EXPERIMENTAL_USE_BUFFER_LOAD_OOB_CHECK_OFFSET_TRICK 0
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#endif
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#ifndef CK_TILE_EXPERIMENTAL_USE_BUFFER_STORE_OOB_CHECK_OFFSET_TRICK
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#define CK_TILE_EXPERIMENTAL_USE_BUFFER_STORE_OOB_CHECK_OFFSET_TRICK 1
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#endif
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#ifndef CK_TILE_EXPERIMENTAL_USE_BUFFER_ATOMIC_ADD_OOB_CHECK_OFFSET_TRICK
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#define CK_TILE_EXPERIMENTAL_USE_BUFFER_ATOMIC_ADD_OOB_CHECK_OFFSET_TRICK 1
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#endif
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#ifndef CK_TILE_EXPERIMENTAL_USE_BUFFER_ATOMIC_MAX_OOB_CHECK_OFFSET_TRICK
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#define CK_TILE_EXPERIMENTAL_USE_BUFFER_ATOMIC_MAX_OOB_CHECK_OFFSET_TRICK 1
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#endif
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#ifndef CK_TILE_USE_AMD_LDS_DIRECT_LOAD_INLINE_ASM
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#define CK_TILE_USE_AMD_LDS_DIRECT_LOAD_INLINE_ASM 1
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#endif
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#ifndef CK_TILE_USE_AMD_BUFFER_LOAD
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#define CK_TILE_USE_AMD_BUFFER_LOAD 1
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#endif
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#ifndef CK_TILE_USE_AMD_BUFFER_STORE
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#define CK_TILE_USE_AMD_BUFFER_STORE 1
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#endif
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#ifndef CK_TILE_USE_AMD_BUFFER_ATOMIC_ADD_INTEGER
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#define CK_TILE_USE_AMD_BUFFER_ATOMIC_ADD_INTEGER 1
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#endif
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#ifndef CK_TILE_USE_PK4_LAYOUT_SHUFFLE
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#define CK_TILE_USE_PK4_LAYOUT_SHUFFLE 1
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#endif
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// buffer atomic add: floating point
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#ifndef __HIP_DEVICE_COMPILE__ // for host code
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#define CK_TILE_USE_AMD_BUFFER_ATOMIC_ADD_FLOAT 1
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#elif defined(__gfx9__) || defined(__gfx12__) // for GPU code
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#define CK_TILE_USE_AMD_BUFFER_ATOMIC_ADD_FLOAT 1
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#else // for GPU code
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#define CK_TILE_USE_AMD_BUFFER_ATOMIC_ADD_FLOAT 0
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#endif
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#if(defined(__gfx90a__) || defined(__gfx94__)) // for GPU code
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#define CK_TILE_USE_AMD_BUFFER_ATOMIC_MAX_FLOAT64 1
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#else
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#define CK_TILE_USE_AMD_BUFFER_ATOMIC_MAX_FLOAT64 0
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#endif
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#ifndef CK_TILE_EXPERIMENTAL_USE_MEMCPY_FOR_VECTOR_ACCESS
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#define CK_TILE_EXPERIMENTAL_USE_MEMCPY_FOR_VECTOR_ACCESS 0
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#endif
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#ifndef CK_TILE_WORKAROUND_SWDEV_XXXXXX_INT8_DS_WRITE_ISSUE
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#define CK_TILE_WORKAROUND_SWDEV_XXXXXX_INT8_DS_WRITE_ISSUE 1
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#endif
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#ifndef CK_TILE_WORKAROUND_ROCM_6_1_SCRATCH_MEMORY_ISSUE
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#if HIP_VERSION_MAJOR == 6 && HIP_VERSION_MINOR == 1 && HIP_VERSION_PATCH >= 40091
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#define CK_TILE_WORKAROUND_ROCM_6_1_SCRATCH_MEMORY_ISSUE 1
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#else
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#define CK_TILE_WORKAROUND_ROCM_6_1_SCRATCH_MEMORY_ISSUE 0
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#endif
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#endif
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// workaround for ROCm 6.2 and later
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#ifndef CK_TILE_WORKAROUND_ROCM_6_2_SCRATCH_MEMORY_ISSUE
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#if(HIP_VERSION_MAJOR == 6 && HIP_VERSION_MINOR == 2 && HIP_VERSION_PATCH >= 41133) || \
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(HIP_VERSION_MAJOR == 6 && HIP_VERSION_MINOR == 3 && HIP_VERSION_PATCH >= 42131) || \
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(HIP_VERSION_MAJOR == 6 && HIP_VERSION_MINOR > 3)
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#define CK_TILE_WORKAROUND_ROCM_6_2_SCRATCH_MEMORY_ISSUE 1
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#else
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#define CK_TILE_WORKAROUND_ROCM_6_2_SCRATCH_MEMORY_ISSUE 0
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#endif
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#endif
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// use llvm builtin bf16 data type after ROCm 6.5
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#ifndef CK_TILE_USE_LLVM_BUILTIN_BF16
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#if(HIP_VERSION_MAJOR == 6 && HIP_VERSION_MINOR == 5 && HIP_VERSION_PATCH >= 50421) || \
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(HIP_VERSION_MAJOR >= 7)
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#define CK_TILE_USE_LLVM_BUILTIN_BF16 1
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#else
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#define CK_TILE_USE_LLVM_BUILTIN_BF16 0
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#endif
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#endif
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#ifndef CK_TILE_DEBUG_LOG
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#define CK_TILE_DEBUG_LOG 0
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#endif
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#ifndef __HIP_DEVICE_COMPILE__ // for host code
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#define CK_TILE_BUFFER_RESOURCE_3RD_DWORD 0xffffffff
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#elif defined(__gfx803__) || defined(__gfx900__) || defined(__gfx906__) || \
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defined(__gfx9__) // for GPU code
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#define CK_TILE_BUFFER_RESOURCE_3RD_DWORD 0x00020000
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#elif defined(__gfx103__) // for GPU code
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#define CK_TILE_BUFFER_RESOURCE_3RD_DWORD 0x31014000
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#elif defined(__gfx11__) || defined(__gfx12__) // for GPU code
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#define CK_TILE_BUFFER_RESOURCE_3RD_DWORD 0x31004000
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#endif
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#ifndef CK_TILE_EXPERIMENTAL_BLOCK_SYNC_LDS_WITHOUT_SYNC_VMEM
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#define CK_TILE_EXPERIMENTAL_BLOCK_SYNC_LDS_WITHOUT_SYNC_VMEM 1
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#endif
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#ifndef CK_TILE_USE_SUBDWORD_TILE_CAST
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#define CK_TILE_USE_SUBDWORD_TILE_CAST 0
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#endif
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#ifndef CK_TILE_USE_PK_FP16_TILE_CAST
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#define CK_TILE_USE_PK_FP16_TILE_CAST 0
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#endif
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// TODO: better solve this inside compiler
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#ifndef CK_TILE_FMHA_FWD_FAST_EXP2
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#define CK_TILE_FMHA_FWD_FAST_EXP2 0
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#endif
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#ifndef CK_TILE_FMHA_FLOAT_TO_FLOAT16_RTN
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#define CK_TILE_FMHA_FLOAT_TO_FLOAT16_RTN 0
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#endif
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#ifndef CK_TILE_BUFFER_LOAD_RAW_BF16_WA
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#define CK_TILE_BUFFER_LOAD_RAW_BF16_WA 1
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#endif
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// workaround: compiler not emiting reciprocal instruction frm __frcp_rn()
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#ifndef CK_TILE_WORKAROUND_SWDEV_383542
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#define CK_TILE_WORKAROUND_SWDEV_383542 1
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#endif
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#ifndef CK_TILE_REFERENCE_MOE_SORTING_MOCK_ID
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#define CK_TILE_REFERENCE_MOE_SORTING_MOCK_ID 1
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#endif
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#ifndef CK_TILE_USE_OCP_FP8
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#if defined(__HIP_DEVICE_COMPILE__)
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#if defined(__gfx950__) || defined(__gfx12__)
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#define CK_TILE_USE_OCP_FP8 1
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#else
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#define CK_TILE_USE_OCP_FP8 0
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#endif
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#else
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#define CK_TILE_USE_OCP_FP8 0
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#endif
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#endif
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#ifndef CK_TILE_USE_BUFFER_ADDRESSING_BUILTIN
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#if __clang_major__ >= 20 && !(defined(__gfx103__) || defined(__gfx11__) || defined(__gfx12__))
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#define CK_TILE_USE_BUFFER_ADDRESSING_BUILTIN 1
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#else
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#define CK_TILE_USE_BUFFER_ADDRESSING_BUILTIN 0
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#endif
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#endif
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#ifndef CK_TILE_WA_ISSUE_2028
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#define CK_TILE_WA_ISSUE_2028 0
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#endif
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// Y pointed to R, we don't see a valuable use case.
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// Will enforce encoding to check Y not pointed to R if set to zero
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#ifndef CK_TILE_ENC_SUPPORT_Y_TO_R
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#define CK_TILE_ENC_SUPPORT_Y_TO_R 0
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#endif
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