mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-05 14:11:29 +00:00
6dfb92bbef
* conv3d compiles but has memory error * conv3d works * fix performance issue by using __builtin_amdgc_readfirstlane * change MakeBlock2CTileMap to MakeDefaultBlock2CTileMap; change c_blockid_to* to cblockid_to* * clang-format * remove CK_EXPERIMENTAL_PASS_TENSOR_DECRIPTOR_BY_*; moved wrapper into DeviceConv3d * format * remove useless marc * add comment Co-authored-by: Chao Liu <chao.liu2@amd.com>
507 lines
21 KiB
C++
507 lines
21 KiB
C++
#ifndef DEVICE_BATCHED_GEMM_XDL_HPP
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#define DEVICE_BATCHED_GEMM_XDL_HPP
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#include <iostream>
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#include <sstream>
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#include "device.hpp"
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#include "device_base.hpp"
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#include "device_gemm.hpp"
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#include "common_header.hpp"
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#include "tensor_layout.hpp"
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#include "tensor_descriptor.hpp"
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#include "tensor_descriptor_helper.hpp"
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#include "gridwise_batched_gemm_xdlops_v2r3.hpp"
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namespace ck {
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namespace tensor_operation {
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namespace device {
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template <typename ADataType,
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typename BDataType,
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typename CDataType,
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typename AccDataType,
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typename ALayout,
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typename BLayout,
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typename CLayout,
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typename AElementwiseOperation,
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typename BElementwiseOperation,
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typename CElementwiseOperation,
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ck::index_t BlockSize,
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ck::index_t MPerBlock,
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ck::index_t NPerBlock,
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ck::index_t K0PerBlock,
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ck::index_t K1,
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ck::index_t MPerXDL,
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ck::index_t NPerXDL,
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ck::index_t MXdlPerWave,
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ck::index_t NXdlPerWave,
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typename ABlockTransferThreadClusterLengths_G_K0_M_K1,
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typename ABlockTransferThreadClusterArrangeOrder,
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typename ABlockTransferSrcAccessOrder,
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ck::index_t ABlockTransferSrcVectorDim,
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ck::index_t ABlockTransferSrcScalarPerVector,
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ck::index_t ABlockTransferDstScalarPerVector_K1,
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bool ABlockLdsAddExtraM,
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typename BBlockTransferThreadClusterLengths_G_K0_N_K1,
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typename BBlockTransferThreadClusterArrangeOrder,
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typename BBlockTransferSrcAccessOrder,
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ck::index_t BBlockTransferSrcVectorDim,
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ck::index_t BBlockTransferSrcScalarPerVector,
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ck::index_t BBlockTransferDstScalarPerVector_K1,
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bool BBlockLdsAddExtraN,
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ck::index_t CThreadTransferSrcDstVectorDim,
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ck::index_t CThreadTransferDstScalarPerVector>
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struct DeviceBatchedGemmXdl
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: public DeviceGemm<AElementwiseOperation, BElementwiseOperation, CElementwiseOperation>
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{
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static constexpr auto I0 = Number<0>{};
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static constexpr auto I1 = Number<1>{};
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static constexpr auto I2 = Number<2>{};
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static constexpr auto I3 = Number<3>{};
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static constexpr auto K1Number = Number<K1>{};
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static auto
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MakeAGridDescriptor_G_K0_M_K1(index_t BatchCount, index_t M, index_t K, index_t StrideA)
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{
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assert(K % K1 == 0);
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const index_t K0 = K / K1;
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const auto a_grid_desc_g_m_k = [&]() {
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if constexpr(is_same<tensor_layout::gemm::RowMajor, ALayout>::value)
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{
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return make_naive_tensor_descriptor(make_tuple(BatchCount, M, K),
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make_tuple(M * StrideA, StrideA, I1));
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}
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else if constexpr(is_same<tensor_layout::gemm::ColumnMajor, ALayout>::value)
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{
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return make_naive_tensor_descriptor(make_tuple(BatchCount, M, K),
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make_tuple(K * StrideA, I1, StrideA));
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}
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}();
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const auto PadM = (MPerBlock - M % MPerBlock) % MPerBlock;
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const auto a_grid_desc_g_k0_mp_k1 =
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transform_tensor_descriptor(a_grid_desc_g_m_k,
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make_tuple(make_pass_through_transform(BatchCount),
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make_unmerge_transform(make_tuple(K0, K1Number)),
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make_right_pad_transform(M, PadM)),
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make_tuple(Sequence<0>{}, Sequence<2>{}, Sequence<1>{}),
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make_tuple(Sequence<0>{}, Sequence<1, 3>{}, Sequence<2>{}));
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return a_grid_desc_g_k0_mp_k1;
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}
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static auto
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MakeBGridDescriptor_G_K0_N_K1(index_t BatchCount, index_t K, index_t N, index_t StrideB)
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{
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assert(K % K1 == 0);
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const index_t K0 = K / K1;
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const auto b_grid_desc_g_k_n = [&]() {
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if constexpr(is_same<tensor_layout::gemm::RowMajor, BLayout>::value)
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{
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return make_naive_tensor_descriptor(make_tuple(BatchCount, K, N),
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make_tuple(K * StrideB, StrideB, I1));
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}
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else if constexpr(is_same<tensor_layout::gemm::ColumnMajor, BLayout>::value)
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{
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return make_naive_tensor_descriptor(make_tuple(BatchCount, K, N),
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make_tuple(N * StrideB, I1, StrideB));
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}
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}();
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const auto PadN = (NPerBlock - N % NPerBlock) % NPerBlock;
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const auto b_grid_desc_g_k0_np_k1 =
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transform_tensor_descriptor(b_grid_desc_g_k_n,
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make_tuple(make_pass_through_transform(BatchCount),
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make_unmerge_transform(make_tuple(K0, K1Number)),
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make_right_pad_transform(N, PadN)),
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make_tuple(Sequence<0>{}, Sequence<1>{}, Sequence<2>{}),
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make_tuple(Sequence<0>{}, Sequence<1, 3>{}, Sequence<2>{}));
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return b_grid_desc_g_k0_np_k1;
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}
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static auto MakeCGridDescriptor_G_M_N(index_t BatchCount, index_t M, index_t N, index_t StrideC)
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{
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const auto c_grid_desc_g_m_n = [&]() {
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if constexpr(is_same<tensor_layout::gemm::RowMajor, CLayout>::value)
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{
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return make_naive_tensor_descriptor(make_tuple(BatchCount, M, N),
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make_tuple(M * StrideC, StrideC, I1));
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}
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else if constexpr(is_same<tensor_layout::gemm::ColumnMajor, CLayout>::value)
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{
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return make_naive_tensor_descriptor(make_tuple(BatchCount, M, N),
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make_tuple(N * StrideC, I1, StrideC));
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}
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}();
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const auto PadM = (MPerBlock - M % MPerBlock) % MPerBlock;
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const auto PadN = (NPerBlock - N % NPerBlock) % NPerBlock;
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const auto c_grid_desc_g_mp_np =
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transform_tensor_descriptor(c_grid_desc_g_m_n,
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make_tuple(make_pass_through_transform(BatchCount),
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make_right_pad_transform(M, PadM),
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make_right_pad_transform(N, PadN)),
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make_tuple(Sequence<0>{}, Sequence<1>{}, Sequence<2>{}),
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make_tuple(Sequence<0>{}, Sequence<1>{}, Sequence<2>{}));
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return c_grid_desc_g_mp_np;
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}
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using AGridDesc_G_K0_M_K1 = decltype(MakeAGridDescriptor_G_K0_M_K1(1, 1, 1, 1));
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using BGridDesc_G_K0_N_K1 = decltype(MakeBGridDescriptor_G_K0_N_K1(1, 1, 1, 1));
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using CGridDesc_G_M_N = decltype(MakeCGridDescriptor_G_M_N(1, 1, 1, 1));
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// GridwiseBatchedGemm
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using GridwiseBatchedGemm = GridwiseBatchedGemm_gk0mk1_gk0nk1_gmn_xdlops_v2r3<
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BlockSize,
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ADataType, // TODO: distinguish A/B datatype
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AccDataType,
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CDataType,
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InMemoryDataOperationEnum_t::Set,
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AGridDesc_G_K0_M_K1,
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BGridDesc_G_K0_N_K1,
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CGridDesc_G_M_N,
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AElementwiseOperation,
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BElementwiseOperation,
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CElementwiseOperation,
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MPerBlock,
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NPerBlock,
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K0PerBlock,
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MPerXDL,
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NPerXDL,
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K1,
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MXdlPerWave,
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NXdlPerWave,
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ABlockTransferThreadClusterLengths_G_K0_M_K1,
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ABlockTransferThreadClusterArrangeOrder,
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ABlockTransferSrcAccessOrder,
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ABlockTransferSrcVectorDim,
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ABlockTransferSrcScalarPerVector,
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ABlockTransferDstScalarPerVector_K1,
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false, // AThreadTransferSrcResetCoordinateAfterRun,
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ABlockLdsAddExtraM,
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BBlockTransferThreadClusterLengths_G_K0_N_K1,
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BBlockTransferThreadClusterArrangeOrder,
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BBlockTransferSrcAccessOrder,
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BBlockTransferSrcVectorDim,
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BBlockTransferSrcScalarPerVector,
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BBlockTransferDstScalarPerVector_K1,
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false, // BThreadTransferSrcResetCoordinateAfterRun,
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BBlockLdsAddExtraN,
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Sequence<0, 1, 3, 5, 6, 7, 2, 4, 8>, // CThreadTransferSrcDstAccessOrder,
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CThreadTransferSrcDstVectorDim,
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CThreadTransferDstScalarPerVector>;
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// Argument
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struct Argument : public BaseArgument
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{
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Argument(const ADataType* p_a_grid,
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const BDataType* p_b_grid,
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CDataType* p_c_grid,
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index_t M,
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index_t N,
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index_t K,
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index_t StrideA,
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index_t StrideB,
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index_t StrideC,
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index_t M01,
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index_t N01,
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AElementwiseOperation a_element_op,
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BElementwiseOperation b_element_op,
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CElementwiseOperation c_element_op,
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index_t BatchCount)
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: p_a_grid_{p_a_grid},
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p_b_grid_{p_b_grid},
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p_c_grid_{p_c_grid},
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a_grid_desc_g_k0_m_k1_{},
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b_grid_desc_g_k0_n_k1_{},
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c_grid_desc_g_m_n_{},
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c_grid_desc_g_m0_n0_m1_n1_m2_m3_m4_n2_{},
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block_2_ctile_map_{},
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M01_{M01},
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N01_{N01},
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a_element_op_{a_element_op},
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b_element_op_{b_element_op},
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c_element_op_{c_element_op}
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{
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a_grid_desc_g_k0_m_k1_ =
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DeviceBatchedGemmXdl::MakeAGridDescriptor_G_K0_M_K1(BatchCount, M, K, StrideA);
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b_grid_desc_g_k0_n_k1_ =
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DeviceBatchedGemmXdl::MakeBGridDescriptor_G_K0_N_K1(BatchCount, K, N, StrideB);
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c_grid_desc_g_m_n_ =
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DeviceBatchedGemmXdl::MakeCGridDescriptor_G_M_N(BatchCount, M, N, StrideC);
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if(GridwiseBatchedGemm::CheckValidity(
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a_grid_desc_g_k0_m_k1_, b_grid_desc_g_k0_n_k1_, c_grid_desc_g_m_n_, M01_, N01_))
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{
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c_grid_desc_g_m0_n0_m1_n1_m2_m3_m4_n2_ =
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GridwiseBatchedGemm::MakeCGridDescriptor_G_M0_N0_M1_N1_M2_M3_M4_N2(
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c_grid_desc_g_m_n_);
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block_2_ctile_map_ =
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GridwiseBatchedGemm::MakeDefaultBlock2CTileMap(c_grid_desc_g_m_n_, M01, N01);
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}
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}
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// private:
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const ADataType* p_a_grid_;
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const BDataType* p_b_grid_;
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CDataType* p_c_grid_;
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AGridDesc_G_K0_M_K1 a_grid_desc_g_k0_m_k1_;
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BGridDesc_G_K0_N_K1 b_grid_desc_g_k0_n_k1_;
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CGridDesc_G_M_N c_grid_desc_g_m_n_;
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typename GridwiseBatchedGemm::CGridDesc_G_M0_N0_M1_N1_M2_M3_M4_N2
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c_grid_desc_g_m0_n0_m1_n1_m2_m3_m4_n2_;
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typename GridwiseBatchedGemm::DefaultBlock2CTileMap block_2_ctile_map_;
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index_t M01_;
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index_t N01_;
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AElementwiseOperation a_element_op_;
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BElementwiseOperation b_element_op_;
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CElementwiseOperation c_element_op_;
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};
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// Invoker
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struct Invoker : public BaseInvoker
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{
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using Argument = DeviceBatchedGemmXdl::Argument;
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float Run(const Argument& arg, int nrepeat = 1)
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{
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{
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std::cout << "arg.a_grid_desc_g_k0_m_k1_{"
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<< arg.a_grid_desc_g_k0_m_k1_.GetLength(I0) << ", "
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<< arg.a_grid_desc_g_k0_m_k1_.GetLength(I1) << ", "
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<< arg.a_grid_desc_g_k0_m_k1_.GetLength(I2) << ", "
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<< arg.a_grid_desc_g_k0_m_k1_.GetLength(I3) << "}" << std::endl;
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std::cout << "arg.b_grid_desc_g_k0_n_k1_{"
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<< arg.b_grid_desc_g_k0_n_k1_.GetLength(I0) << ", "
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<< arg.b_grid_desc_g_k0_n_k1_.GetLength(I1) << ", "
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<< arg.b_grid_desc_g_k0_n_k1_.GetLength(I2) << ", "
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<< arg.b_grid_desc_g_k0_n_k1_.GetLength(I3) << "}" << std::endl;
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std::cout << "arg.c_grid_desc_g_m_n_{" << arg.c_grid_desc_g_m_n_.GetLength(I0)
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<< ", " << arg.c_grid_desc_g_m_n_.GetLength(I1) << ", "
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<< arg.c_grid_desc_g_m_n_.GetLength(I2) << "}" << std::endl;
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}
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if(!GridwiseBatchedGemm::CheckValidity(arg.a_grid_desc_g_k0_m_k1_,
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arg.b_grid_desc_g_k0_n_k1_,
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arg.c_grid_desc_g_m_n_,
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arg.M01_,
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arg.N01_))
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{
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throw std::runtime_error(
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"wrong! GridwiseBatchedGemm_km_kn_m0m1n0n1_xdlops_v2r3 has invalid setting");
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}
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const index_t grid_size =
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GridwiseBatchedGemm::CalculateGridSize(arg.c_grid_desc_g_m_n_);
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const auto K0 = arg.a_grid_desc_g_k0_m_k1_.GetLength(I1);
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const bool has_main_k0_block_loop =
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GridwiseBatchedGemm::CalculateHasMainK0BlockLoop(K0);
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float ave_time = 0;
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if(has_main_k0_block_loop)
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{
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const auto kernel = kernel_batched_gemm_xdlops_v2r3<
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GridwiseBatchedGemm,
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ADataType, // TODO: distiguish A/B datatype
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CDataType,
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remove_reference_t<DeviceBatchedGemmXdl::AGridDesc_G_K0_M_K1>,
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remove_reference_t<DeviceBatchedGemmXdl::BGridDesc_G_K0_N_K1>,
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remove_reference_t<
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typename GridwiseBatchedGemm::CGridDesc_G_M0_N0_M1_N1_M2_M3_M4_N2>,
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AElementwiseOperation,
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BElementwiseOperation,
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CElementwiseOperation,
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remove_reference_t<typename GridwiseBatchedGemm::DefaultBlock2CTileMap>,
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true>;
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ave_time = launch_and_time_kernel(kernel,
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nrepeat,
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dim3(grid_size),
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dim3(BlockSize),
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0,
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arg.p_a_grid_,
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arg.p_b_grid_,
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arg.p_c_grid_,
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arg.a_grid_desc_g_k0_m_k1_,
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arg.b_grid_desc_g_k0_n_k1_,
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arg.c_grid_desc_g_m0_n0_m1_n1_m2_m3_m4_n2_,
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arg.a_element_op_,
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arg.b_element_op_,
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arg.c_element_op_,
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arg.block_2_ctile_map_);
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}
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else
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{
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const auto kernel = kernel_batched_gemm_xdlops_v2r3<
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GridwiseBatchedGemm,
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ADataType, // TODO: distiguish A/B datatype
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CDataType,
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remove_reference_t<DeviceBatchedGemmXdl::AGridDesc_G_K0_M_K1>,
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remove_reference_t<DeviceBatchedGemmXdl::BGridDesc_G_K0_N_K1>,
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remove_reference_t<
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typename GridwiseBatchedGemm::CGridDesc_G_M0_N0_M1_N1_M2_M3_M4_N2>,
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AElementwiseOperation,
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BElementwiseOperation,
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CElementwiseOperation,
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remove_reference_t<typename GridwiseBatchedGemm::DefaultBlock2CTileMap>,
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false>;
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ave_time = launch_and_time_kernel(kernel,
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nrepeat,
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dim3(grid_size),
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dim3(BlockSize),
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0,
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arg.p_a_grid_,
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arg.p_b_grid_,
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arg.p_c_grid_,
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arg.a_grid_desc_g_k0_m_k1_,
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arg.b_grid_desc_g_k0_n_k1_,
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arg.c_grid_desc_g_m0_n0_m1_n1_m2_m3_m4_n2_,
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arg.a_element_op_,
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arg.b_element_op_,
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arg.c_element_op_,
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arg.block_2_ctile_map_);
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}
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return ave_time;
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}
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// polymorphic
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float Run(const BaseArgument* p_arg, int nrepeat = 1) override
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{
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return Run(*dynamic_cast<const Argument*>(p_arg), nrepeat);
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}
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};
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static constexpr bool IsValidCompilationParameter()
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{
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// TODO: properly implement this check
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return true;
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}
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static bool IsSupportedArgument(const Argument& arg)
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{
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return GridwiseBatchedGemm::CheckValidity(arg.a_grid_desc_g_k0_m_k1_,
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arg.b_grid_desc_g_k0_n_k1_,
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arg.c_grid_desc_g_m_n_,
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arg.M01_,
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arg.N01_);
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}
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// polymorphic
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bool IsSupportedArgument(const BaseArgument* p_arg) override
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{
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return IsSupportedArgument(*dynamic_cast<const Argument*>(p_arg));
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}
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static auto MakeArgument(const ADataType* p_a,
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const BDataType* p_b,
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CDataType* p_c,
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index_t M,
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index_t N,
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index_t K,
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index_t StrideA,
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index_t StrideB,
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index_t StrideC,
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AElementwiseOperation a_element_op,
|
|
BElementwiseOperation b_element_op,
|
|
CElementwiseOperation c_element_op,
|
|
index_t BatchCount)
|
|
{
|
|
return Argument{p_a,
|
|
p_b,
|
|
p_c,
|
|
M,
|
|
N,
|
|
K,
|
|
StrideA,
|
|
StrideB,
|
|
StrideC,
|
|
1,
|
|
1,
|
|
a_element_op,
|
|
b_element_op,
|
|
c_element_op,
|
|
BatchCount};
|
|
}
|
|
|
|
static auto MakeInvoker() { return Invoker{}; }
|
|
|
|
// polymorphic
|
|
std::unique_ptr<BaseArgument> MakeArgumentPointer(const void* p_a,
|
|
const void* p_b,
|
|
void* p_c,
|
|
index_t M,
|
|
index_t N,
|
|
index_t K,
|
|
index_t StrideA,
|
|
index_t StrideB,
|
|
index_t StrideC,
|
|
AElementwiseOperation a_element_op,
|
|
BElementwiseOperation b_element_op,
|
|
CElementwiseOperation c_element_op,
|
|
index_t BatchCount) override
|
|
{
|
|
return std::make_unique<Argument>(static_cast<const ADataType*>(p_a),
|
|
static_cast<const BDataType*>(p_b),
|
|
static_cast<CDataType*>(p_c),
|
|
M,
|
|
N,
|
|
K,
|
|
StrideA,
|
|
StrideB,
|
|
StrideC,
|
|
1,
|
|
1,
|
|
a_element_op,
|
|
b_element_op,
|
|
c_element_op,
|
|
BatchCount);
|
|
}
|
|
|
|
// polymorphic
|
|
std::unique_ptr<BaseInvoker> MakeInvokerPointer() override
|
|
{
|
|
return std::make_unique<Invoker>(Invoker{});
|
|
}
|
|
|
|
// polymorphic
|
|
std::string GetTypeString() const override
|
|
{
|
|
auto str = std::stringstream();
|
|
|
|
// clang-format off
|
|
str << "DeviceBatchedGemmXdl"
|
|
<< "<"
|
|
<< BlockSize << ", "
|
|
<< MPerBlock << ", "
|
|
<< NPerBlock << ", "
|
|
<< K0PerBlock
|
|
<< ">";
|
|
// clang-format on
|
|
|
|
return str.str();
|
|
}
|
|
};
|
|
|
|
} // namespace device
|
|
} // namespace tensor_operation
|
|
} // namespace ck
|
|
#endif
|