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https://github.com/ROCm/composable_kernel.git
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920acd2c12
[CK] [CK_Tile] Add GroupConv to Kernel Dispatcher ## Motivation This PR adds CK Tile group convolution (forward, backward-data, backward-weight) support to the kernel dispatcher, matching and unifying with the existing dispatcher GEMM infrastructure in architecture and usability. The dispatcher provides a unified kernel dispatch system with both C++ and Python frontends, and until now only supported GEMM operations. This PR enables framework integrators to use the same declarative kernel workflow for convolutions as they do for GEMM: declare kernels, build a registry JIT, select kernels within the registry at runtime, and dispatch to GPU. Future PRs will include runtime kernel selection heuristics for autotuning of kernel parameters based on (problem, hardware arch). ## Technical Details Grouped convolution support has been added to the CK Tile Dispatcher with generated_conv_backend.hpp enabling dispatcher.run(in, wei, out, problem) for all 6 conv variants (fwd/bwdd/bwdw x 2D/3D), runtime heuristic kernel selection, and GroupedConvKernelKey with full ConvConfigBase fields. Python side adds parallel JIT via registry.build(max_workers) and heuristic registry.select(). Includes 7 C++ and 6 Python examples covering all directions with CPU reference validation, and shared infrastructure improvements (BaseRegistry CRTP, structured exceptions). As a sanity check, JIT compile times for a single kernel remains the same and for multiple kernels there is better parallelism: Kernels | 1 worker | 8 workers 1 | 7.7 s | 7.7 s 2 | 15.9 s | 8.2 s 4 | 33.4 s | 9.7 s 6 | 52.3 s | 10.2 s ## Test Plan 145 ephemeral unit tests have been added to test basic functionality. All 30 examples/integration tests run end-to-end on gfx950 (MI350): 7 C++ conv, 7 C++ GEMM, 6 Python conv, 10 Python GEMM. CPU reference validation for forward, backward-data, and backward-weight (2D) in both C++ and Python examples pass. ## Test Result 30 examples pass. Peak performance: 132 TFLOPS (Batch-32 forward 56x56), 53 TFLOPS (pointwise 1x1). CPU reference accuracy: max_abs_diff < 0.002 for all directions (fp16 vs fp32 reference). ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.
245 lines
8.9 KiB
Python
245 lines
8.9 KiB
Python
#!/usr/bin/env python3
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# Copyright (c) Advanced Micro Devices, Inc., or its affiliates.
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# SPDX-License-Identifier: MIT
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"""
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Tests for codegen/codegen_common.py -- shared infrastructure for GEMM and grouped conv codegen.
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Phase 1a TDD: these tests are written BEFORE the implementation exists.
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Run: python3 -m pytest tests/test_codegen_common.py -v
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"""
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import sys
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import unittest
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from pathlib import Path
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SCRIPT_DIR = Path(__file__).parent.resolve()
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DISPATCHER_DIR = SCRIPT_DIR.parent
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sys.path.insert(0, str(DISPATCHER_DIR / "codegen"))
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from codegen_common import ( # noqa: E402
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TileConfig,
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TraitConfigBase,
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CommonTypeMappings,
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generate_cpp_compilation_unit,
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parallel_generate,
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valid_wave_configs,
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valid_warp_configs,
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valid_trait_configs,
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needs_wave_expansion,
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needs_warp_expansion,
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needs_pipeline_expansion,
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)
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class TestTileConfig(unittest.TestCase):
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"""TileConfig dataclass tests."""
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def test_valid_config(self):
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tc = TileConfig(128, 128, 32, 2, 2, 1, 32, 32, 16)
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self.assertTrue(tc.is_valid())
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def test_zero_tile_invalid(self):
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tc = TileConfig(0, 128, 32, 2, 2, 1, 32, 32, 16)
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self.assertFalse(tc.is_valid())
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def test_non_divisible_invalid(self):
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tc = TileConfig(127, 128, 32, 2, 2, 1, 32, 32, 16)
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self.assertFalse(tc.is_valid())
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def test_all_fields_accessible(self):
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tc = TileConfig(256, 128, 64, 4, 1, 1, 32, 32, 16)
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self.assertEqual(tc.tile_m, 256)
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self.assertEqual(tc.tile_n, 128)
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self.assertEqual(tc.tile_k, 64)
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self.assertEqual(tc.warp_m, 4)
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self.assertEqual(tc.warp_n, 1)
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self.assertEqual(tc.warp_k, 1)
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self.assertEqual(tc.warp_tile_m, 32)
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self.assertEqual(tc.warp_tile_n, 32)
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self.assertEqual(tc.warp_tile_k, 16)
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def test_small_valid_config(self):
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tc = TileConfig(16, 16, 16, 1, 1, 1, 16, 16, 16)
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self.assertTrue(tc.is_valid())
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class TestTraitConfigBase(unittest.TestCase):
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"""TraitConfigBase dataclass tests."""
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def test_valid_intrawave(self):
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tc = TraitConfigBase("compv3", "cshuffle", "intrawave", False, False, False)
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self.assertTrue(tc.is_valid())
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def test_invalid_interwave_compv3(self):
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tc = TraitConfigBase("compv3", "cshuffle", "interwave", False, False, False)
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self.assertFalse(tc.is_valid())
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def test_invalid_interwave_compv4(self):
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tc = TraitConfigBase("compv4", "cshuffle", "interwave", False, False, False)
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self.assertFalse(tc.is_valid())
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def test_valid_mem_interwave(self):
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tc = TraitConfigBase("mem", "cshuffle", "interwave", False, False, False)
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self.assertTrue(tc.is_valid())
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def test_valid_mem_intrawave(self):
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tc = TraitConfigBase("mem", "cshuffle", "intrawave", False, False, False)
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self.assertTrue(tc.is_valid())
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def test_padding_fields(self):
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tc = TraitConfigBase("compv3", "cshuffle", "intrawave", True, True, True)
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self.assertTrue(tc.pad_m)
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self.assertTrue(tc.pad_n)
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self.assertTrue(tc.pad_k)
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class TestCommonTypeMappings(unittest.TestCase):
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"""CommonTypeMappings tests."""
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def test_dtype_to_ck(self):
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self.assertEqual(CommonTypeMappings.DTYPE_TO_CK["fp16"], "fp16_t")
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self.assertEqual(CommonTypeMappings.DTYPE_TO_CK["bf16"], "bf16_t")
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self.assertEqual(CommonTypeMappings.DTYPE_TO_CK["fp32"], "float")
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self.assertEqual(CommonTypeMappings.DTYPE_TO_CK["fp8"], "fp8_t")
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def test_pipeline_to_ck(self):
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self.assertEqual(
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CommonTypeMappings.PIPELINE_TO_CK["mem"], "GemmPipelineAgBgCrMem"
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)
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self.assertIn("compv3", CommonTypeMappings.PIPELINE_TO_CK)
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self.assertIn("compv4", CommonTypeMappings.PIPELINE_TO_CK)
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def test_pipeline_to_base(self):
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self.assertIn("mem", CommonTypeMappings.PIPELINE_TO_BASE)
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self.assertIn("compv3", CommonTypeMappings.PIPELINE_TO_BASE)
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self.assertIn("compv4", CommonTypeMappings.PIPELINE_TO_BASE)
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def test_scheduler_to_ck(self):
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self.assertIn("intrawave", CommonTypeMappings.SCHEDULER_TO_CK)
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self.assertIn("interwave", CommonTypeMappings.SCHEDULER_TO_CK)
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def test_epilogue_to_dispatcher(self):
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self.assertIn("cshuffle", CommonTypeMappings.EPILOGUE_TO_DISPATCHER)
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self.assertIn("default", CommonTypeMappings.EPILOGUE_TO_DISPATCHER)
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def test_layout_to_ck(self):
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self.assertIn("r", CommonTypeMappings.LAYOUT_TO_CK)
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self.assertIn("c", CommonTypeMappings.LAYOUT_TO_CK)
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def test_get_output_dtype(self):
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self.assertEqual(CommonTypeMappings.get_output_dtype("fp8"), "fp16")
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self.assertEqual(CommonTypeMappings.get_output_dtype("bf8"), "fp16")
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self.assertEqual(CommonTypeMappings.get_output_dtype("fp16"), "fp16")
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self.assertEqual(CommonTypeMappings.get_output_dtype("fp32"), "fp32")
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class TestGenerateCppCompilationUnit(unittest.TestCase):
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"""Tests for generate_cpp_compilation_unit."""
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def test_includes_kernel_header(self):
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result = generate_cpp_compilation_unit("my_kernel")
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self.assertIn('#include "my_kernel.hpp"', result)
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def test_contains_pragma_once_or_guard(self):
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result = generate_cpp_compilation_unit("test_kernel")
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self.assertIn("test_kernel", result)
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def test_different_names_different_output(self):
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a = generate_cpp_compilation_unit("kernel_a")
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b = generate_cpp_compilation_unit("kernel_b")
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self.assertNotEqual(a, b)
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class TestParallelGenerate(unittest.TestCase):
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"""Tests for parallel_generate helper."""
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def _dummy_generate(self, item):
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return f"generated_{item}"
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def test_parallel_returns_all(self):
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items = ["a", "b", "c", "d"]
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results = parallel_generate(self._dummy_generate, items, parallel=True)
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self.assertEqual(len(results), 4)
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for item in items:
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self.assertIn(f"generated_{item}", results)
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def test_sequential_returns_all(self):
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items = ["x", "y", "z"]
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results = parallel_generate(self._dummy_generate, items, parallel=False)
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self.assertEqual(len(results), 3)
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for item in items:
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self.assertIn(f"generated_{item}", results)
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def test_empty_items(self):
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results = parallel_generate(self._dummy_generate, [], parallel=True)
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self.assertEqual(len(results), 0)
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def test_logs_per_kernel_progress(self):
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items = ["k1", "k2"]
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with self.assertLogs(level="INFO") as cm:
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parallel_generate(self._dummy_generate, items, parallel=False)
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log_output = "\n".join(cm.output)
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self.assertIn("k1", log_output)
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self.assertIn("k2", log_output)
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class TestArchAwareExpansion(unittest.TestCase):
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"""Tests for arch-aware expansion helpers (best-of-conv)."""
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def test_valid_wave_configs_gfx942(self):
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configs = valid_wave_configs("gfx942")
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self.assertIsInstance(configs, list)
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self.assertIn([2, 2, 1], configs)
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self.assertIn([1, 4, 1], configs)
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def test_valid_wave_configs_unknown_arch(self):
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configs = valid_wave_configs("gfx_unknown")
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self.assertIsInstance(configs, list)
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self.assertGreater(len(configs), 0)
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def test_valid_warp_configs_gfx942_fp16(self):
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configs = valid_warp_configs("gfx942", "fp16")
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self.assertIsInstance(configs, list)
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self.assertIn([32, 32, 16], configs)
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def test_valid_warp_configs_unknown_arch(self):
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configs = valid_warp_configs("gfx_unknown", "fp16")
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self.assertIsInstance(configs, list)
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self.assertGreater(len(configs), 0)
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def test_valid_trait_configs_excludes_interwave_compute(self):
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configs = valid_trait_configs()
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self.assertIsInstance(configs, list)
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self.assertNotIn(("compv3", "cshuffle", "interwave"), configs)
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self.assertNotIn(("compv4", "cshuffle", "interwave"), configs)
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def test_valid_trait_configs_includes_mem_interwave(self):
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configs = valid_trait_configs()
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has_mem_interwave = any(p == "mem" and s == "interwave" for p, s in configs)
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self.assertTrue(has_mem_interwave)
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def test_needs_wave_expansion_wildcard(self):
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self.assertTrue(needs_wave_expansion({"wave_m": -1, "wave_n": 2}))
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self.assertTrue(needs_wave_expansion({"wave_m": 2, "wave_n": -1}))
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def test_needs_wave_expansion_explicit(self):
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self.assertFalse(needs_wave_expansion({"wave_m": 2, "wave_n": 2}))
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def test_needs_warp_expansion_wildcard(self):
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self.assertTrue(needs_warp_expansion({"warp_m": -1, "warp_n": 32}))
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def test_needs_warp_expansion_explicit(self):
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self.assertFalse(needs_warp_expansion({"warp_m": 32, "warp_n": 32}))
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def test_needs_pipeline_expansion_wildcard(self):
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self.assertTrue(needs_pipeline_expansion({"pipeline": "*"}))
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def test_needs_pipeline_expansion_explicit(self):
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self.assertFalse(needs_pipeline_expansion({"pipeline": "compv4"}))
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if __name__ == "__main__":
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unittest.main()
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